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Hi All,
Quartus has stopped generating an automatically generated timing constraint file after Quartus 14.0 and I am having problems in constraining the 1000Mbps Small Mac. The design is fully constrained but there are a lot of irregularities relating to the RX Clock of the Mac. If anyone has an example .sdc file to share it would be a great help or just guide me through constraining the Mac. Thanks in advanceLink Copied
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The timing constraints will be very dependent on what type of external Ethernet interface you are using - i.e gmii/sgmii/rgmii/transceiver etc.
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--- Quote Start --- The timing constraints will be very dependent on what type of external Ethernet interface you are using - i.e gmii/sgmii/rgmii/transceiver etc. --- Quote End --- Yes that much I understand and the interface I'm using for my external Ethernet is rgmii.
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--- Quote Start --- Yes that much I understand and the interface I'm using for my external Ethernet is rgmii. --- Quote End --- You might have a look at this example from Altera. http://www.altera.com/support/examples/interfaces-peripherals/exm-tse-rgmii-phy.html However, as I recall the Ethernet independent examples in Time Quest User's Guide follow on for source synchronous timing are a good place to start. http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

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