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Altera_Forum
Honored Contributor I
1,084 Views

Timing constraints for 2 clocks, phase shifted by 90 degrees

Hello all,  

 

I have a design, in which two clocks are used. One main clock and another one with 90 degree fixed phase shift. There are registers that are related to these clocks, for example regA clocked by main_clk is connected to the regB clocked by clk90.  

How can I set the correct timing constraints in this case? Is there any available literature for this subject? 

 

Thanks in advance.
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4 Replies
Altera_Forum
Honored Contributor I
69 Views

Assuming both clocks are coming from a PLL, first create your base (reference) clock into the device. Then use derive_pll_clocks to create the clock constraints. If you're not using a PLL, you'll need to use create_generated_clock in your .sdc file. See these online trainings for details: 

 

https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=tim... 

 

(If URL doesn't work, put "timing" or "timing analyzer" in the filter.)
Altera_Forum
Honored Contributor I
69 Views

Thanks for your answer.  

Do you know if I need synchronizers between these clock domains?
Altera_Forum
Honored Contributor I
69 Views

Not if you can achieve regular timing closure between the synchronous domains. The original question makes only sense if this is your intention.

Altera_Forum
Honored Contributor I
69 Views

Ok. Thanks.

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