Hello all,I have a design, in which two clocks are used. One main clock and another one with 90 degree fixed phase shift. There are registers that are related to these clocks, for example regA clocked by main_clk is connected to the regB clocked by clk90. How can I set the correct timing constraints in this case? Is there any available literature for this subject? Thanks in advance.
Assuming both clocks are coming from a PLL, first create your base (reference) clock into the device. Then use derive_pll_clocks to create the clock constraints. If you're not using a PLL, you'll need to use create_generated_clock in your .sdc file. See these online trainings for details:https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=tim... (If URL doesn't work, put "timing" or "timing analyzer" in the filter.)