Timing constraints to use with EPCQ128A on Cyclone10 LP Evaluation Board

[MMacg]

Hello. I have been trying to constrain four paths that are being reported as unconstrained in Timing Analyzer in Quartus Standard as shown below:

nios:nios_i|nios_epcq_controller2_0:epcq_controller2_0|nios_epcq_controller2_0_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_DATA

nios:nios_i|nios_epcq_controller2_0:epcq_controller2_0|nios_epcq_controller2_0_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_DCLK

nios:nios_i|nios_epcq_controller2_0:epcq_controller2_0|nios_epcq_controller2_0_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_SCE

nios:nios_i|nios_epcq_controller2_0:epcq_controller2_0|nios_epcq_controller2_0_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_SDO

I am using the cyclone 10 LP evaluation board and I am trying to implement the guidance from this previous post about constraining timing for the Serial Flash Loader. https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd02172015_590.html

Unfortunately, it doesn't really tell you the clock rate is is assuming, setup and hold values of the destination SPI device and the board trace delay. Intel mention that you need to modify these values based upon your own design. However, it's difficult to assign my own values as the example doesn't tell you how they arrived at their values for the set_input_delay and set_output_delay.

The EPCQ core in the nios system I am using should really constrain this interface but it is not from what I can see. Has anyone had any success constraining an EPCQ interface?

Thanks

[KhaiChein_Y_Intel]

Hi,

May I request the design for investigation? What is the software edition and version you are using?

Thanks.

[MMacg]

Hi YY, You can recreate the issue using this example design posted on the Intel support forums: https://forums.intel.com/s/question/0D50P000043euVGSAY/cyclone-10-lp-evaluation-kit-not-booting-nios-from-epcq-flash?language=en_US The file is attached in the second last comment window called C10LP_NIOS2. If you compile the design you should see the following unconstrained paths reported: SYSTEM:u0|SYSTEM_PERIPHERALS:peripherals|SYSTEM_PERIPHERALS_EPCQ64:epcq64|SYSTEM_PERIPHERALS_EPCQ64_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_DATA0 No input delay, min/max delays, false-path exceptions, or max skew assignments found SYSTEM:u0|SYSTEM_PERIPHERALS:peripherals|SYSTEM_PERIPHERALS_EPCQ64:epcq64|SYSTEM_PERIPHERALS_EPCQ64_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_DCLK No output delay, min/max delays, false-path exceptions, or max skew assignments found SYSTEM:u0|SYSTEM_PERIPHERALS:peripherals|SYSTEM_PERIPHERALS_EPCQ64:epcq64|SYSTEM_PERIPHERALS_EPCQ64_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_SCE No output delay, min/max delays, false-path exceptions, or max skew assignments found SYSTEM:u0|SYSTEM_PERIPHERALS:peripherals|SYSTEM_PERIPHERALS_EPCQ64:epcq64|SYSTEM_PERIPHERALS_EPCQ64_asmi2_inst_epcq_ctrl:asmi2_inst_epcq_ctrl|altera_asmi2_qspi_interface:asmi2_qspi_interface_0|altera_asmi2_qspi_interface_asmiblock:dedicated_interface|dut_asmiblock~ALTERA_SDO No output delay, min/max delays, false-path exceptions, or max skew assignments found I am using Quartus Prime Standard Edition 18.1.0 Build 625 09/12/2018 SJ. Thanks MMG

[KhaiChein_Y_Intel]

Hi,

The signal delay from FPGA or flash memory device to the PFL synchronous input port is specified by set_input_delay. The delay calculation is:

Input delay value = Board delay from FPGA or flash output port to the PFL input port + TCO of the FPGA or flash memory device

The signal delay from PFL synchronous output port to FPGA or flash memory device is specified by set_output_delay. The delay calculation is:

Output delay value = Board delay from the PFL output port to the FPGA or flash input port + TSU of FPGA or flash device.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf Chapter 1.4.2.2. Constraining Synchronous Input and Output Ports 

Thanks.

[MMacg]

Hi YY,

thanks for the response and for the clarification of the timing constraints.

Cheers

MMG

[KhaiChein_Y_Intel]

Hi,,

No problem.

Thanks.