Timing requirements to a part of a circuit

[Altera_Forum]

Does anybody know how to set timing requirements to a part of a circuit? I mean there is a critical part of a circuit that needs frequency optimization, and it's not rational to apply frequency constraint to all block. Thanks in advance.

[Altera_Forum]

--- Quote Start ---  I'm just trying different possible approaches. That was my mistake when I used set_multicycle_path and set_max_delay at the same time. Yes, you are right, multicycle relaxes constraints. I'm thinking that in some situations we can use set max delay just to constraint one or several data paths rather then using multicycle together with clock constraint  --- Quote End ---    set_min_delay and set_max_delay: These constraints can emulate multicycle constraints. set_max_delay overrides SMC and set_min_delay overrides HMC. For example SMC of 2 and HMC of 1 means set_max_delay to 2 clock periods and set_min_delay to 0 clock period. However, delay values are in time units rather than clock periods and so can be defined with higher resolution.

[Altera_Forum]

Tricky, fortunatelly, my project (I mean my real project, not example from the cookbook) works normally with current clk frequency (96 MHz - fast version and just 24 MHz - slow version). However, in some cases I use such chains like reg (clk,ena)->logic->reg (clk)->logic->reg(ena,clk). Here I use reg(clk) just to divide long logic chain into two parts (I guess it facilitates routing). Multicycle analysis isn't applicable here. TA warns me and shows negative slacks for such circuits, because it takes all these regs as regs(clk). What I do is control delays in this paths by myself and make sure that slacks are OK . Of, course, as long as my project works I'll not do any tedious work :) But I would like to study how to use TA because it's a useful thing. 

 kaz, is it enough for a simple project just two lines for sdc file: create_clock -period 10.000 -waveform {0.000 5.000} -name fast_clk [get_ports {fast_clk}] set_max_delay -from [get_pins inst21 [*]|q] -to [get_pins inst24 [*]|d] 20  ? If I use 2 ns instead of 20 there will be no timing error.  Thank you both for your support.

[Altera_Forum]

--- Quote Start ---   kaz, is it enough for a simple project just two lines for sdc file: create_clock -period 10.000 -waveform {0.000 5.000} -name fast_clk [get_ports {fast_clk}] set_max_delay -from [get_pins inst21 [*]|q] -to [get_pins inst24 [*]|d] 20  ? If I use 2 ns instead of 20 there will be no timing error.  Thank you both for your support.  --- Quote End ---    Your path inst21 to inst24 is enabled once every two clocks so apply multicycle (if it is failing), not set max delay