Re: Timing simulation

Altera_Forum · ‎02-07-2011

Hi,

I'm having problems with timing simulation in Modelsim. I compile and sythesize in Precision and I do the map and route in Quartus. Once I have the .sdo, .vho and testbench files I tried to do the simulation but I have the next errors in relation with the .sdo file.

#  Loading work.cycloneii_lcell_comb(vital_lcell_comb)#1
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(35): Failed to find INSTANCE '/testbench/iCLK_50_ibuf/asynch_inst'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(44): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(53): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\/extena0_reg'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(68): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/inreg_D_mux'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(77): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/input_reg'.
#  ** Warning: (vsim-SDF-3432) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: This file is probably applied to the wrong instance.
#  Ignoring subsequent missing instances from this file.
#  ** Warning: (vsim-SDF-3440) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: Failed to find any of the 23 instances from this file.
#  ** Warning: (vsim-SDF-3442) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: Try instance '/testbench/dut'. It contains all instance paths from this file.
#  Error loading design

I have read other posts but I don't find any solution, if someone can guide me a little.

Many thanks

Altera_Forum · ‎02-07-2011

The error log says that some instances are not found.

Did you check that they're present in the design files?

Your post is entitled 'timing simulation'. Do you mean that RTL simulation is working for the same design?

Altera_Forum · ‎02-07-2011

does RTL simulation work?

i would try and avoid paths with spaces, but i'm not sure that's the root cause

Altera_Forum · ‎02-14-2011

Hi,

I have tried to find a solution but I'm not capable. The RTL simulation goes perfectly, the problem starts when I introduce the .sdo file. I continue with the same errors

# ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(35): Failed to find INSTANCE '/testbench/iCLK_50_ibuf/asynch_inst'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(44): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(53): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\/extena0_reg'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(68): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/inreg_D3656_mux'.
#  ** Error: (vsim-SDF-3250) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(77): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/input_reg'.
#  ** Warning: (vsim-SDF-3432) D:/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: This file is probably applied to the wrong instance.

I thinks that the problem is that I don't give the correct path to the instance, as this links comments: http://www.altera.com/support/kdb/solutions/rd05152000_7434.html. I tried to show the path in : SDF--> APPLY TO REGION showing the .vho file.

Anyone can suggest me the correct way to do this

Many thanks

Altera_Forum · ‎02-14-2011

Hi,

I have made a little step. The problem is that the .sdo file used internal signals declare in .vho file. So I suppose that I have to include the .vho file inside the testbench but I don't know how, I comment this because in Modelsim in the gap: "Apply to region" I have to sugget the name of the intetity of the testbench, so should be a connection between files. And also I have to do the timing simulation without warnings.

Many thanks