Hi,I am receiving lots of timing violations on signals crossing clock domains to SignalTap II Analyzer. Should I set false path to all the signals connected to the SignalTap II analyzer? Thanks, Hua
You need to treat signaltap as any logic inside the fpga for that is what it is.The timing must not be violated or else your samples would be unreliable. You should use the same data clock (or a faster synchronised clock) to sample your data, so you don't need to cross from data domain to signaltap domain.
As far as I know, the embedded logic analyser has one sampling clock. Hence there is no reliable way to sample data from different clk domains.Intersting point...why altera doesn't add more sampling clocks?
kaz is right that you should only be sampling data in the same domain as your signaltap. I have had cases where I need to get that data but also look at data in another domain. It would naturally fail timing, but I was fine with that and didn't bother cutting it. The data captured had to be carefully analyzed, since I knew I would be sampling during transitions, but it works.
If I added signals from multiple clock domains to the signal tap clock domain and the TimeQuest detected those violations during fitting, would those time violations somehow affect the fitter making bad decision on placement and/or routing?
If you have unrealistic requirements, the fitter will still try to meet them(it has no idea what's realistic). It's possible that could hurt your real requirements, although more often than not it won't. You need to analyze your failing paths. If the only failing paths are these ones you would expect to fail, then it didn't hurt, but if other paths suddenly fail and they're part of your design, then that's a problem.
You can create multiple instances in a single stp file that all run on different clocks. Right click in the instance manager and select "create instance". The different instances operate seperately, so you can't trigger one based on the signal of another, but you can however bring out multiple clock domains into a single stp file.Kevin
If timing violations are related to signal tap, would deleting .stp file be the best thing to do, assuming that I don't need signal tap anymore. Signal tap is for debugging, not for real operation.
Am I correct?