Does the following verilog correctly pulse a reset pin?input [15:0]shadow; input tach; input carry_in; output [15:0]active; output reset; reg [15:0]active; reg reset; always@(negedge tach) begin active = shadow; reset = 1;
reset = 0;
end Please help? Additonally, Is there an overall better way to do this? Basically I am trying to count the total time a input square wave is high. So when it goes high, I start my counter. The above module does not show the counter, just the output transition module. As it transitions back to low, I want to 1.) copy the count from the counter 'shadow' to another register 'active' 2.) clear the counter to 0 Any advice?
--- Quote Start --- Does the following verilog correctly pulse a reset pin? --- Quote End --- According to Verilog rules, it doesn't pulse anything, just performs reset=0. To control a counter and store it's value on a particular event, you better design a synchronous state machine operating with the counted clock.