I have tried to test the signal integrity with Stratix IV GT (EP4S100G2F40I1). The design examples are downloaded from Transceiver Link Debugging Using the Quartus II Software. I tried with both "siv_GT_1ch_40b_11300mbps", and "siv_GT_4ch_40b_10312mbps" and followed the instruction from the Transceiver Link Debugging Using the System Console. But there are several issues during the run:
In case serial loopback is enabled:
For the 1 channel design, the RX CDR PLL is not locked so that the status is yellow and blinking. I do not know how to fix this.
In case the serial loopback is not enabled:
I created a new link using SMA cables with transmitter and receiver either on the same board or in two different boards. The problem here is that the received signal (number of bit tested and error bits and BER) is strange in a way that sometimes the number of bit tested changes, sometimes not and the BER is usually very high. Then, when I changed the cables, the result is still the same.
So, if anyone has experienced the same or you have any suggestion about the reason or some advice. If possible, please help to show me the exact type of SMA cable/connector that works best with my Stratix IV GT board.
Thanks alot.
