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When implementing GIGE on CycloneV transceiver using Custom Phy is needed to perform "running disparity rules" on FPGA logic outside transceiver phy?
I think the answer is yes, but I would to check with experts ;-) Thank you!Link Copied
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Are you referring to running disparity checking? If I remember it correct the Custom PHY has this function available where it will flag error when running disparity is incorrect. The output status port is rx_disperr.
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thank you! I will check them.
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Yes. If you transmit even length packet, the FCS must be followed by /T/R/ (tx_paralleldata = 16'hFDF7, tx_datak = 2'b11). If you transmit odd length frames, the FCS must be followed by /T/R/R/ (tx_paralleldata = 24'hFDF7F7, tx_datak = 3'b111).
BTW, the GIGE mode is tricky. You should go through AN537 if you plan to use 1000BASE-X/SGMII Auto-Negotiation. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an537.pdf- Mark as New
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Ok, so I need to transmit control codes on the line and check if extra /R/ is need based on even/odd packet but PCS will check running disparity to perform 8b/10b job.
e.g., I'm on sync phase and want to transmit data 8'hAA. I will send a /S/ 8'hAA /T/R/R ((tx_paralleldata = 40'hFBAAFDD7D7 ) , tx_datak = 5'b10111)) and then check if rx_disperr still no error. It is correct? Cheers! ps. I'm not planning auto negotiation for now :)- Mark as New
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Hi kkaibara,
Thanks for sharing the AN.- Mark as New
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Yes, correct. If I test the phy, I monitor rx_runningdisp and rx_errdetect status signals too. Because the running disparity of K28.5 in IDLE code (/I/) must be minus disparity (rx_runningdisp = 1).
The simple test pattern will be /I/I/I/I/I/I/I/I/S/8'hAA/T/R/R/I/I/I/I/I/I/I/I. rx_disperr and rx_errdetect should be low, and rx_runningdisp should be high when rx_paralleldata = 8'hBC, tx_datak = 1'b1.- Mark as New
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Thank you kkaibara this helps me a lot.
I will run this test pattern when I write sync state machine. ;-) cheers!- Subscribe to RSS Feed
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