I am using Arria 10 development board.
In my design I am using Arria 10 transceiver in Native PHY mode.
I have integrated transceiver + reset controller + fpll as arria 10 transceiver user guide.
When bitstream is flashed I see transmit clock being generated by fpll.
When I press reset button and release it then fpll stops generating transmit clock. I believe that reset controller is not releasing powerdown signal to fpll.
I have a free running reference clock.
Any thoughts on why fpll is not generating transmit clock when reset button is pressed ?
Thanks & Regards,