Hi everyone,
I'm seeing something strange and wanted to see if anyone else has seen something like this. I've got two Arria V GZ FPGAs connected by a transceiver link running at 12Gbps. We've added logic to generate and check PRBS which we can enable on the fly to overwrite our normal data.
If we reset the receiver only, we can get a significantly different error rate which changes after each successive reset. The range is on the order of a few to 100s per second. We're not quite sure how resetting just the receiver is causing this.
For some background, we're using the Native PHY, transceiver reconfiguration controller, and transceiver reset controller. The reset we're toggling is the input to the reset controller which sequences the analog and digital reset into the PHY. We have the ability to change analog settings by writing into the reconfiguration controller but we're not using that right now.
Thanks for looking!
