[Transceiver toolkit] Reference clock trouble

[Altera_Forum]

Software: Quartus II 13.1 (64bit) 

Device: 5SGXE7N2F40C2 Kit: Stratix V GX Edition Transceivr Sigal Integrity Kit PC OS : Windows server 2012 64bit & windows 7 64bit  Nice to mee you. My name is Alex, and I just begin studying FPGA. I've bought Stratix IV & V for using transceiver toolkit, and overwritten the IV's Qsys to the V's Qsys by mistake. (I've never thought that those transceivers have different structure) After that, V's toolkit doesn't work. Precisely, Compiling and Programming have no problem, but in toolkit window, pll lock of transmitters doesn't activate. So, I requested to engineer in authorized distribution co., and he said reference clock has problem. And also, he commmended to find other repairing vendors.  Before I call the engineer, I want to know that any solutions about this problem. Is there anyone who suffered this kinds of trouble?

[Altera_Forum]

Hi Alex, 

 you can find Transceiver Toolkit designs for Stratix V in the Altera Wiki: http://www.alterawiki.com/wiki/transceiver_toolkit (http://www.alterawiki.com/wiki/transceiver_toolkit)  One of these should get you back to a working state.

[Altera_Forum]

The Stratix V and Stratix IV has discrepancy in term of the transceiver architecture and IP. Thus, the IV's qsys and V's qsys can not be interchange. You could also download the transceiver toolkit design examples provided by Altera from https://www.altera.com/support/support-resources/design-examples/design-software/on-chip-debugging.html. Here you can find different design example for different devices and Quartus II version.