Triple Speed Ethernet (TSE) MAC without/built-in PHY

[Altera_Forum]

Hi Everyone, 

 I was wondering if there is an alternative to built a system to use ethernet 1 Gbps only without or buillt-in quartus PHY. The TSE uses PHY to make the ethernet signals. I think if there is a PHY to interface the TSE MAC inside an Altera chip. The main idea is to use some lvds pin (like 8 pins) to use with a RJ45 + Magnetics.  Anybody tryed to do such thing?:confused:  Is there someone to give a hint?:confused:   Thanks all, Nosima

[Altera_Forum]

Most people don't use the built-in phy. Just configure the TSE MAC for GMII instead. 

 Jake

[Altera_Forum]

Hi Jacob, 

 But using TSE MAC for GMII I need a PHY right? I've heard that I can use TSE MAC without PHY. Is there right?  nosima

[Altera_Forum]

Well what is it you are trying to accomplish? If you are going to drive a regular ethernet cable on a regular network then yes you need a PHY.  

 If you are simply going to communicate with two FPGAs on a board or over a backplane then you might have some more options. At some level you need some sort of PHY (but depending on what you are trying to accomplish, you might be able to write it yourself).

[Altera_Forum]

Hi Jacob, 

 I want to try to drive a regular ethernet directly into a Altera pin. But you answered me, I need to use a PHY always.  Thanks!

[Altera_Forum]

Hi, 

 I tried to send packet from MAC to PHY using RGMII interface. Somehow, there is no packet being sent. I tried to do loopback or MAC. Again, i notice that there is no packet being sent and received. I have configured MAC using registers in Nios II software. Can anyone tell me what shud i check for this issue?  Thanks, Caridee

[Altera_Forum]

What hardware do you have? Did you use a ready made .sof file?

[Altera_Forum]

I'm using the Altera Triple Speed Ethernet IP with cyclone iii, and trying to test the Rx and Tx of 10/100/1000 Ethernet MAC(RGMII). The test is done as following: 

1- setting the loop_ENA bit in command_config register to 1 and  2-comparing the statistics counters aFramesTransmittedOK and aFramesReceivedOK to verify that the transmit and receive frame counts are equal. 3-checking the statistics counters ifInErrors and ifOutErrors to determine the number of packets transmitted and received with errors. According to the attached file named"Triple Speed Ethernet User Guide" So, kindly send me a design example made using the SOPC Builderto perform the internal MAC local loopback on it.

[Altera_Forum]

hi...,my name is dileep kumar,and here iam trying to access (TSE-ipcore)ethernet in cyclone iii,so can u just tell me how to start..i mean can u please provide any example for a basic start...

[Altera_Forum]

Hi, 

 I realize this is an old thread, but this discussion is about my question so I do not see any reason to create a new thread with the same subject. Basically, my question has already been asked, but I do not think there is given a clear answer, so I thought I would give it a try again.  scenario:  I am planning to use two Altera Cyclone V GX FPGAs, which I would like to communicate via Ethernet. The two FPGAs are going to be placed on the same board. I want to use the Triple-Speed Ethernet IP core, and I would like to use a SGMII interface. This means I plan to use the following configuration:  https://www.alteraforum.com/forum/attachment.php?attachmentid=7304   question: In most scenarios that I have seen the SGMII interface interfaces to a PHY (with a SGMII interface), or in other cases the communication is MAC-to-PHY (without the PCS and PMA). From what I understand, the PHY provides a feature called auto-negotiation among other things.  however, since i am using a point-to-point connection between two fpgas is it not possible to hard-code information like link-speed, half/full duplex mode and etc., which otherwise would be exchanged and set in accordance to the auto-negotiation? so, i am asking the same question again, does anyone know/has anyone tried to see if it is possible to have a mac-to-mac communication, if used in a point-to-point connection between two fpgas on the same board?   The reason I do not want to use a PHY is the fact that a PHY consumes a lot of power and I do not need to communicate with an optical or copper platform. Finally, I want to use the SGMII interface, because of its low power, low pin count and differential pair for data and clock.   Thank you in advance,

[Altera_Forum]

You might get better luck with some gurus answering by creating a new topic instead of this old one. 

 For what it's worth, I haven't done what you would like, but I believe it is done commonly in backplanes. Here is one semi-relevant appnote, your application is Figure 2, substituting another FPGA instead of the SFP like in Figure 10.  http://www.altera.com/literature/an/an518.pdf  Good luck!