TrustZone prevents access to CoreSight

[Altera_Forum]

To change any of the CoreSight memory mapped registers, I have to use the DAP debug bus. For example: 

 mem set APB:0x80007000 0 1  will enable the FPGA-CTI.  I can see the change from HPS bus if I do:  x SP:0xff007000  but I can not write with   mem set SP:0xff007000 0 1  This is a TrustZone issue as I can't even see the memory from normal world, NP:.  Although there is a workaround for the debugger by using APB:, this causes me grief when I try to read or write CoreSight memory locations (remapped via mmap, running as root) in software. How do I disable TrustZone for the CoreSight memory locations? Or how do I enable secure reads/writes to these locations?  I am using Quartus 13.1. My info mem appears below. I am using very slightly extended GSRD and GHRD.   Thanks,  Steve Haynal  1: y SP:0x00000000 SP:0xFFFFFFFF rw, nocache, verify Memory accessed using secure world physical addresses 16: y S:0x00000000 S:0x7EFFFFFF nobp Linux application address space 2: y S:0x00000000 S:0xFFFFFFFF rw, nocache, verify Memory accessed using secure world addresses 7: y S:0x80008000 S:0x800081BF cache [.head.text]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 8: y S:0x800081C0 S:0x8045B297 cache [.text]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 9: y S:0x805EDDEC S:0x805EDE0F cache [.notes]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 10: y S:0x805EE000 S:0x8060D04F cache [.init.text]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 11: y S:0x8060D050 S:0x8060E27F cache [.exit.text]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 12: y S:0x806145C0 S:0x8062BFBB cache [.init.data]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 13: y S:0x8062C000 S:0x8062EC3F cache [.data..percpu]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 14: y S:0x80630000 S:0x8066A497 cache [.data]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 15: y S:0x8066A4C0 S:0x806A2C7F cache [.bss]/home/shaynal/local/altera/13.1/embedded/embeddedsw/socfpga/prebuilt_images/vmlinux 3: y NP:0x00000000 NP:0xFFFFFFFF rw, nocache, verify Memory accessed using normal world physical addresses 4: y N:0x00000000 N:0xFFFFFFFF rw, nocache, verify Memory accessed using normal world addresses 5: y APB:0x00000000 APB:0xFFFFFFFF rw, nobp, nohbp, nocache, noverify APB bus accessed via AP_1 on DAP_0 6: y AHB:0x00000000 AHB:0xFFFFFFFF rw, nobp, nohbp, nocache, noverify AHB bus accessed via AP_0 on DAP_0

[Altera_Forum]

Did you unlock the coresight components (in your case, FPGA-CTI) before trying to access it through the core?  

 The lock register is at 0x80007fb0 and the value to be written is 0xc5acce55. You can either do this through DAP or through your core (0xff007fb0) before trying to do any mem write to coresight.