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Altera_Forum
Honored Contributor I
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UART using LOAN on DE10 Nano

hi everyone, i'm Ivan 

 

 

i'm working with a de10 nano and i'm trying to communicate by UART to my computer using LOAN IO for use only this HPS's pheripheral. I've created the system in Qsys and it compiles in "Analisys & Synthesis"but in the "Fitter (Place & Route)" part i got a problem cause appear this message: 

 

 

error (21179): pins memory_mem_ck and memory_mem_ck_n form a differential pair and uses pseudo-differential output node uart_3_hps_0:hps_0|uart_3_hps_0_hps_io:hps_io|uart_3_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator|pseudo_diffa_0. however, these pins also have an i/o standard 2.5 v that cannot be supported by the pseudo-differential output node. 

 

 

what i have to do to can compile? 

Somebody can help me please? 

Thanks
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1 Reply
Altera_Forum
Honored Contributor I
68 Views

Hi, 

 

I guess you're facing this issue due to the fact that the tool has recognized the clock and its inverted version clk_n to be a differential pair and has assigned a pseudo-differential output pin constraint on them. To get past this issue, you need to check if these clocks really form a differential pair or not and then assign them to the appropriate voltage and signal standard aka Differential IO or single-ended. If there are pin constraints already set in by default clear them, run the processes again and see if the tool will assign the correct pins/standards. 

 

If this fails, then manually assign the correct IO and voltage standard to the pins and run it again.
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