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Valued Contributor III
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UP3 Education Board generated sound???

i am trying to use up3 board to generate sound and having problem to connect the speaker to the fpga.i mean which port should i connect the speaker to on the board?:confused:  

 

i am using verilog hdl which i get from www.fpga4fun.com like below.... 

------------------------------------- 

module music(clk, speaker); 

input clk; 

output speaker; 

 

// Binary counter, 16-bits wide 

reg [15:0] counter; 

always @(posedge clk) counter <= counter+1; 

 

// Use the highest bit of the counter (MSB) to drive the speaker 

assign speaker = counter[15]; 

 

endmodule 

-------------------------------- 

 

thank you!!:) :)
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Valued Contributor III
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Re: UP3 Education Board generated sound???

Same Problem, :( 

I am a new person to FPGA Hardware control and i want to access the Speaker in my NEEK evaluation Board. But i cant understand the literature in ALTERA,  

i'am a person of learning by examples not Theories and its costing me a Lot 

 

Any one please give me a example of producing a Beep sound in NEEk, i can develop from that. 

 

Thanks in Advance...:)
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