URGENT: Peripheral to Memory DMA Transaction

[Altera_Forum]

Hello, may I know how to transfer data from peripheral to memory using DMA? It is quite confusing from memory-to-memory transfer. please help! thanks!

[Altera_Forum]

A RAM1port needs address inputs to decide what data to access. A fifo just gives you the first one (remember: first in, first out). 

So, a FIFO looks just like any other register of your periphereal, but queues incoming or outgoing data. That's why it's your choice here.

[Altera_Forum]

I see... so it is not suitable to use ram1 port, as it will be mem to mem transfer, am i right? 

 so, for FIFO, if so, is it like transfer one data at a time?

[Altera_Forum]

1. yes. 

2. no. The reason for the fifo is that you can wait for a number of values to be processed, and fetch them all in one DMA transfer.

[Altera_Forum]

i see.. thanks... besides how do i know how many number of values already being processed and will be transfer by dma?

[Altera_Forum]

have a look at usedw / usedr. 

(Take care that these might be one bit too few, depending on configuration)

[Altera_Forum]

ok. will try it later... might ask u if encounter problem..

[Altera_Forum]

I have read through the pdf regarding FIFO. I have a few questions. 

 1. I need 3 FIFO, for data x, data y and result, am I right? 2. Once i have all the 3 FIFO, how do i integrate them with my peripherals? 3. Since there is no address in FIFO, how does DMA transfer data from it?

[Altera_Forum]

1. yes. 

3. how are you doing it now? I suspect you have one register for each value? 2. drop the fifo between the avalon and your periphereal. You will need to implement the read and write signals on the periphereal side on your own. at the avalon side you can connect what you already have.

[Altera_Forum]

yes, x, y and result have FIFO each respectively... besides, since i am using dcfifo, i have 2 clocks, trclk and rvclk. what are trclk and rvclk? is it connect to main system clock, clk?

[Altera_Forum]

If your periphereal does not use a different clock, you might use a scfifo. 

It might increase resource usage to use a dcfifo and connect both clocks to the same system clock, but yes, that should be no problem.

[Altera_Forum]

now i think i understand... correct me if i am wrong: 

 i connect two FIFO to x and y respectively, then 1 FIFO to result. the former 2 FIFO are connected to avalon bus. and the later FIFO is connected to DMA. am i right?  when i see the pdf regarding FIFO, in the sample design, they use write control logic and read control logic, where FIFO is in between both logic. do i need write and read control logic in this context?

[Altera_Forum]

i have done configuring my scFIFO. i exclude the signal full, empty and usedw, but i did enable the circuitry protection. is it ok? FIFO block has 4 inputs (clk, data, rdreq and wrreq) and 1 output (q). is it ok? thanks!  

 P/S: data is 32 bit and the deep the FIFO should be is 131072 words (256K). Is it ok? Besides, I have one uncertainty here. The FIFO, will it be full? It is a buffer, once it is full with data, will it override itself with new data, or i have to override or reset it manually?

[Altera_Forum]

Good to see you're making progress :-) 

 Yes, the fifo might overrun if you feed it too much data, or underrun if it is empty. I have seen strange behaviour when writing to a full fifo or reading from an empty one; the behaviour in such case is not defined.  Normally, you would read the usedw through another register, and estimate how much data you can read or write in your DMA. Also, one normally connects full/empty to an interrupt line to tell you when you need to react on it. The logic in your periphereal normally also needs to stop stransmission when the fifo is full resp. empty. But for testing it is sufficient to just use it so.  In my design, I use a comparator with a threshold register, so I get an interrupt when the fifo is more or less half full.

[Altera_Forum]

Thanks! So, for the time being, I just stick to my setting: data is 32bit, deep of FIFO 131072 words (will it be too big?), exclude 'full, empty and usedw' signal but enable circuit protection.  

 besides, how to connect the full/empty signal to interrupt line? can it be done in VHDL code only? eg: like full = 1, then de-assert the chipselect of the peripheral.  thanks!

[Altera_Forum]

Basically, that is possible, but you might want te have some logic to acknowledge and suppress the interrupt (Set/Reset register). Otherwise your software might re-enter the interrupt as long as the signal is active.

[Altera_Forum]

Hi, I was trying to integrate everything now but the logic you meant to control the interrupt, is it a interface that I have to write using VHDL?

[Altera_Forum]

You don't have to, it was just a comment for further improvement.

[Altera_Forum]

When i try to compile, i received this error: Error: Selected device has 105 RAM location(s) of type M4K. However, the current design needs more than 105 to successfully fit. why?

[Altera_Forum]

I have done with the connection. But the result i got is weird. i am not sure what is the problem. could you pls help me to check? pls see the attachment. thanks! 

 Notes:  When address is '0', the adder will write the data (writedata) to be calculated, and when '1', adder will send calculated data (readdata) to result.

[Altera_Forum]

Did you set your reset to high? 

 assign reset = 1'b1;

[Altera_Forum]

why reset is high? i thought reset = 0 for the system to work.