USB Blaster, Cyclone III, PS question

[Altera_Forum]

For development work, I would like to use a USB Blaster to configure a Cyclone III device in Passive Serial mode. Most of the USB Blaster is powered from the USB's VBUS except the I/O pins that connect to the target which are powered from a supply on the target board instead. Figure 9-18 of the Cyclone III FPGA Family Handbook shows the set up. It shows the USB Blaster's I/O power pin (pin 4 of the 10 pin connector) connected to VCCA. But VCCA is 2.5V and all my I/O pins are powered by 3.3V. According to the USB Blaster datasheet, its I/O buffer can handle 1.8V to 5.0V so why does Figure 9-18 specify connecting the USB Blaster power to VCCA and not VCCIO? 

 Also, if it does need to be connected to VCCA instead, if I'm also going to eventually end up using a micro to program the FPGA in PS mode, do I need to use VCCA for the micro's I/O levels instead of 3.3V? The standard PS configuration Figure 9-14 for example would indicate that I should use VCCIO instead.  Thanks! -Randy

[Altera_Forum]

--- Quote Start ---  I would like to use a USB Blaster to configure a Cyclone III device in Passive Serial mode  --- Quote End ---   It's not supported by the Quartus programmer tool, what do you want to achieve?

[Altera_Forum]

Really?  

 Table 1-1 of the USB Blaster Download Cable User guide says about the Passive Serial Mode: "Configures all Altera devices supported by Quartus II software excluding MAX 3000, MAX 7000, MAX II, EPC enhanced configuration devices, and EPCS serial configuration devices."  I'm actually just using it as a comparison and a means of debugging my microcontroller code that will ultimately be used to program the Cyclone device on my board. I want look at its output and compare it with what my code is doing to hopefully see what I'm doing wrong.  Thanks, -Randy

[Altera_Forum]

--- Quote Start ---  Really?  --- Quote End ---    The Quartus Programmer "Mode" pull-down can be used to select "Passive Serial" mode, so that will probably do what you want. I've never seen a board with a PS header though, they either have JTAG or AS headers, so this feature may or may not work correctly :)    --- Quote Start ---   I'm actually just using it as a comparison and a means of debugging my microcontroller code that will ultimately be used to program the Cyclone device on my board. I want look at its output and compare it with what my code is doing to hopefully see what I'm doing wrong.   --- Quote End ---    Here's some details that might help:  http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf  Cheers, Dave

[Altera_Forum]

Dave- 

 Thanks, I just discovered that paper earlier today. I will definitely check into it.  I'm not going to put a PS header on the board, that would be a bit goofy wouldn't it? As I said, it's only for development, so I'm going to stick some short flywires down and connect them to a header until I can get the micro to load the FPGA.  This being the case, I still don't have an answer to my original question. Why does the Cyclone III manual say to connect the USB Blaster to VCCA instead of VCCIO?  Thanks, -Randy

[Altera_Forum]

--- Quote Start ---   I'm not going to put a PS header on the board, that would be a bit goofy wouldn't it? As I said, it's only for development, so I'm going to stick some short flywires down and connect them to a header until I can get the micro to load the FPGA.  This being the case, I still don't have an answer to my original question. Why does the Cyclone III manual say to connect the USB Blaster to VCCA instead of VCCIO?   --- Quote End ---    Read the handbook for details:  http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf  p165 "Configuration and JTAG Pin I/O Requirements"  - lots of warnings about overshoot on the JTAG signals  - be careful your flying leads do not have ringing on them  p206: "The TDO output pin is powered by VCCIO in I/O bank 1. All the JTAG input pins are powered by the VCCIO pin. All the JTAG pins support only LVTTL I/O standard."  p207: "Because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from VCCA, and you must pull TCK to ground."  Altera recommend you use VCCA = 2.5V so that the USB-Blaster cable drives 2.5V logic levels, which if they over-shoot provide a little more margin than if you'd powered the cable from 3.3V. A robust board design would actually include buffers right at the 10-pin header so that the USB-Blaster signals are not directly driving the FPGA pins.  In your case, measure the signals with a scope. If you source terminate your flying leads, you should be able to eliminate ringing.  Cheers, Dave