USB & EMAC I/O options

[Altera_Forum]

Is it possible to route the HPS USB I/O signals through the FPGA instead of using the dedicated HPS pins? In 13.1 you can only select HPS I/O pin multiplexing for the USB controllers. I'm guessing this is a software restriction rather than a physical restriction in the device? 

 Also, I need to access the PTP clock signals for one of the EMAC interfaces, and these are only available when FPGA pin multiplexing is selected. I am using the HPS set. Is there a way of exposing just the relevant signals to the FPGA while keeping the MII interface on the HPS pins?  Thanks.

[Altera_Forum]

--- Quote Start ---    Also, I need to access the PTP clock signals for one of the EMAC interfaces, and these are only available when FPGA pin multiplexing is selected. I am using the HPS set. Is there a way of exposing just the relevant signals to the FPGA while keeping the MII interface on the HPS pins?   --- Quote End ---    I think, there is RGMII interface when you use dedicated HPS pins and I'm afraid we are'nt abe to access to the P2P clock when we use dedicated IOs. If you need P2P interface you have to use GMII full set through FPGA and FPGA IOs. One more idea, cannot you use GMII interface through FPGA logic and transceiver to reduce interface to RGMII (SGMII,...)?

[Altera_Forum]

I am in the same situation, looking to route the PTP interface to the FPGA and keep the data interface to the HPS I/O. 

 According to the Cyclone V Handbook, chapter 17 EMAC: 

• figure 17-1 - EMAC System Integration  
• and table 17-4 - EMAC to FPGA IEEE1588 Timestamp Interface  
• and the various info in the document  

 we should be able to ONLY expose the timestamp interface (PTP clock, PPS output and AUX timestamp trigger) to the FPGA and keep the MAC interface to HSP I/O.  Hoping there is a way to do that :) Could someone from Altera shed some lights on that?  Thanks

[Altera_Forum]

Have you tryed to connect EMAC through FPGA yet? I've tryed to connect EMAC to the FPGA logic, there make some data changes and route them back to EMAC RX channel. It works but at first, I've problems with data clocking. I connect emac_gtx_clk_out to the emac_rx_clk_in and emac_tx_clk_in but data wasnt benn synchronous with this clock (taken by the Signal Tap). Then I connect emac_gtx_clk_out to the PLL (1:1) and PLL outputs was source for emac_rx_clk_in and emac_tx_clk_in. Then the data leaving EMAC to the FPGA was synchronous with emac_tx_clk_in. Why I need PLL? Is there some documentation with this problematics? 

 I must add that the EMAC was set from Linux at 1 Gbps. TX works (verified by Signal Tap) but receiving doesn't work (DMA initialization problem in EMAC module).  Thanks Milan

[Altera_Forum]

For the EMAC routing to the FPGA and HPS pins are both valid options. For USB you can only route to the HPS pins because the USB protocol does not allow you to add any delay (so pipelining those signals in the FPGA is out of the question). The EMAC doesn't have this issue because you can pipeline the EMAC interface into the FPGA fabric without breaking the protocol. 

 Milan, for the RX issue if you have not already done so I recommend opening a service request to track that issue if it comes from the hardware libraries or Linux drivers.

[Altera_Forum]

Regarding the routing of the EMAC, I have not tried yet as I do not get the function of the loan IO signals (loan_io_in/out/oe hps_io_hps_io_gpio_inst_LOANIO20). What do each signal represent? I did not find any documentation on it. Also, did you use a GMII to RGMII converter? If yes, could you point me to the IP you used? 

 I saw in an other thread (http://www.alteraforum.com/forum/showthread.php?t=41652&highlight=loan+io) that Loan IO are only for low speed signals. In this case, as Milan mentionned, EMAC at 1 Gbps may not work.