Unable to see the falling edge pulse in Quartus simulator

[Altera_Forum]

A very short falling edge pulse will be generated in the test_out output port during rtl simulation in modelsim ase 6.5b. However, I cannot see this short pulse in Quartus II simulator during functional simulation. Is there any settings I should do in Quartus II simulator in order to be able to see this short pulse? Pls refer to attach screenshot for more details. 

 I would appreciate if you could response me asap. Thanks...

[Altera_Forum]

--- Quote Start ---   I would appreciate if you could response me asap. Thanks...  --- Quote End ---   Use this signal as a clock for SignalTap.

[Altera_Forum]

It looks like a glitch, that is most likely ignored in functional simulation. You should try timing simulation to see, if it's actually there. It may be a case of different results between simulation and synthesis, however. If the signal is sourced from combinational logic, it must be generally expected to have glitches, when more than one input terms are changing simultaneously.

[Altera_Forum]

Hi FvM, 

 Thanks for fast response. I agree with you. But, I still do not see a glitch during timing simulation. I found out this seems like the limitation of Max II devices. I can see a glitch in timing simulation if I used cyclone II devices. In cyclone II, I can enable glitch filtering option (assignement-->settings-->simulator settings-->glitch filtering option). However, in max II, the glitch filtering option is gray (inactive).    Question: Is this settings caused me unable to see a glitch during timing simulation? or is there any different in term of settings in max II and cyclone II?   Thanks in advance.....

[Altera_Forum]

Are you sure that the glitch is real? It may be a simulation artefact as well. Most likely it depends on accidental delays, so you can't predict, if it will be present or not. What's your problem in this regard exactly? MAX II and Cyclone are basically using the same (FPGA) synthesis tool and have similar chip technology. I don't expect much differences.

[Altera_Forum]

Hi Fvm, 

 Thanks again for your quick response...   Yes, I tried to produce a glitch in my simple test design. I appreciate if you can spend some time to look at my design and help me to see what is actually wrong here...It is very simple only. my intention is to produce a glicth testing... Actually, my design using Max3000A..Sorry for giving you wrong info previously..It is not max II but is max3000A.    Why I cannt see a glitch on max3000A but I can see it on cyclone II? Is it accidental delays on cyclone II only????

[Altera_Forum]

Using a CPLD makes the difference, because it apparently utilizes a different synthesis tool. You have to set "IGNORE LCELL BUFFERS" to off additionally to keep logic cells, then you get the intended result. 

http://www.alteraforum.com/forum/showthread.php?t=22110  By the way, checking the previous synthesis result at the gatelevel with the netlist viewer tool easily reveals, why it can't work. It's quite different from the FPGA netlist.

[Altera_Forum]

Thanks alot FvM.