I have taken the Terasic TRDB D5M 5MP camera reference design for the Altera DE2-115 development board and written a testbench with a basic model for the camera to send pixel data. When I start the simulation I get the following warnings:# ** Warning: (vsim-3017) ../v/Line_Buffer.v(74): [TFMPC] - Too few port connections. Expected 7, found 6.# Time: 0 ps Iteration: 0 Instance: /ccd_capture_tb/dut_rgb2raw/L1/ALTSHIFT_TAPS_component File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/altera_mf.v# ** Warning: (vsim-3722) ../v/Line_Buffer.v(74): [TFMPC] - Missing connection for port 'sclr'. The Line_Buffer.v contains instance of altshift_taps. The file is attached to this post. I do not understand why this warning is being generated. I am using ModelSim 10.5b that came with download of Quartus Prime 16.1. I opened the design in Quartus Prime and regenerated all the IP files as well to they are up to date.
That warning can usually be safely ignored. It means that one or more ports on the module wasn't connected to something which in many cases is fully intentional.You haven't explained what you mean by "unable to simulate". Such warnings will not stop the simulation running.