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Altera_Forum
Honored Contributor I
772 Views

Unconstrained Path in PFL IP core

Hallo 

 

I am making a PFL IP core for a MAX V device. and i wrote a SDC file based on the application note 478,the PFL IP core user guide. which is available on the following link. I used table 7 from the link to set the clock, set false path and set output delay for the paths. 

 

https://www.altera.com/documentation/sss1411439280066.html#sss1458191622012 

 

But i can still see that some paths are still not constrained, and some paths are partially constrained. Like the flash address [0-20] & flash data [0-15] are suggested to set as false path in the user guide, but after setting them to false path i can still see them in the unconstrained paths list. What could be the reason for this? Am i wrong with the commands i write to set them as a false path? 

 

I am attaching the SDC file that i generated from Timing analyzer tool. can you please have a look and suggest me what changes are necessary.
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2 Replies
Altera_Forum
Honored Contributor I
34 Views

Could you post the output of the Timing analyzer, complete file. It will help in finding out which path is unconstrained.

Altera_Forum
Honored Contributor I
34 Views

i am attaching my whole project file here. maybe this helps with the settings and everything