Understanding Clocks for Arria II

[Altera_Forum]

I am trying to understand the clock signal of the Arria II. What I want to know is: 

1. Is there one main clock input signal for the entire chip? 2. Or is there up to 8 main PLL inputs that drive the entire chip? 3. What is the input frequency range of the main clock.   I have been looking through the Datasheets, 694 pages worth, on page 1-11 of the overview of the Arria II section, it talks about Clock Management and global clock networks. Where it states the Global Clock Networks and eight PLL, but I cannot find anything on a single main input clock signal. Any assistance on this would be helpful.   James

[Altera_Forum]

What you really need is to read chapter 5: Clock Networks and PLLs in Arria II devices. 

 But to get you started: The FPGA has a number of clock input pins; each clock input pins can drive a few GCLK networks; ANY of the GCLK networks can drive logic all over the chip.  So, if all you need is one clock and no PLLs, you just need to connect your clock to one of the clock input signals.  Each clock input pin can also drive two PLLs (see table 5-6 and 5-7). If you only want to use up to two PLLs and you don't care about which ones, then you need to do no more than above.  If you want to use more than 2 PLLs or you care about which PLLs you'll use, then you'll have to look into table 5-6 or 5-7 and connect your clock signal to more than one clock input pin.  Or you can just connect your clock signal to every clock input pin. It also works well.  Then you have the transceivers. If you want to use those, you'll need to provide clocks though the transceivers clock input pins. Read the Transceiver Clocking chapter for that part.

[Altera_Forum]

Thank you rbugalho for your insight. Your comments gave me a better understanding of the clock input. I spent some time reading Chapter 5, which brought up more questions than answers.  

 I understand that there are clock input pins that can drive the GCLK network clocks, but how do I what the input frequency spectrum is? I could not find a Input Clock Frequency Range, in Chapter 5, I did find in Chapter 1, under the PLL Clock Management section :   "Supports spread-spectrum input clocking and counter cascading with PLL input clock frequencies ranging from 5 to 500MHz to support both low-cost and high-end clock performance".   Can I assume that this in my Input Clock frequencies as well?

[Altera_Forum]

There's no minimum clock frequency for the FPGA; only for the PLLs (and transceivers). 

 As for maximum clock frequency, it's a bit more complicated. I think the FPGA input clock pins will accept clocks up to 500 MHz, but only with differential I/O standards. With single ended (ie, LVCMOS), the maximum frequency will be lower.   And the maximum frequency at which your design will be able to operate will depend on your design and on the FPGA's speed grade.   What you need to do is to synthesize your design (with I/O assignments) and see the timing report. If you don't have a prototype of your design, try to create a simple mock up.

[Altera_Forum]

Thanks rbugalho, your comments are appreciated. This helps a lot.