Unwanted behavior of fitter when implemented carry chain

[VMots]

Dear Sirs!

I have a situation when I trying to optimize timing through using curry chain. 

I am using the fiftyfivenm_lcell_comb primitive for this.

When this primitives are inside the one module they are implemented as expected.

But when source and sink lay in different modules quartus do next thing:

it insert additional buffer on the output where cout path goes on standard routing and then from standard routing path to cin which is add additional daley and consequently slack is negative.

I want to ask is anyway to deny this behavior?

FPGA family - MAX10

Quartus version Standard 18.1.1

Thank you in advance

[SyafieqS]

Hi Viktar,

Is optimize timing mean want to close timing?

You can easily add FF to close timing or use Quartus setting compiler to tweak for timing.

[SyafieqS]

Viktar,

Let me know if there is any update or concern.

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.