I have a situation when I trying to optimize timing through using curry chain.
I am using the fiftyfivenm_lcell_comb primitive for this.
When this primitives are inside the one module they are implemented as expected.
But when source and sink lay in different modules quartus do next thing:
it insert additional buffer on the output where cout path goes on standard routing and then from standard routing path to cin which is add additional daley and consequently slack is negative.
I want to ask is anyway to deny this behavior?
FPGA family - MAX10
Quartus version Standard 18.1.1
Thank you in advance
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