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Hold timing fail on a 2FF synchroniser

NShan12
New Contributor I
301 Views

Hello, 

 

I have a 2FF synchroniser for an active LOW asynchronous write signal driven by a Microcontroller. The code is as below:

 

PROCESS (clk, clearn)
BEGIN
IF clearn = '0' THEN
         wrn_dd <= '1';
         wrn_d <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
         wrn_d <= wrn ;
         wrn_dd <= wrn_d;
END IF;
END PROCESS;

 

After running full compilation Timing analyser throws a Hold timing error from node wrn_d to node wrn_dd (only in the Fast timing corner). Why is this happening and how can it be solved?

 

My understanding is: Clock to Q delay of a flip flop in FPGA is such that it does not cause hold violation at the next connected flip flop. If this is true then why is a hold violation occuring in this case?

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5 Replies
sstrell
Honored Contributor III
286 Views

What do your SDC constraints look like for the clock and the (I'm presuming) wrn input (set_input_delay)?  And do you have a false path on clearn?

NShan12
New Contributor I
279 Views

Hi, 

I have create clock command on clk (32 MHz) and false path set on both wrn and clearn inputs.

wrn and clearn are asynchronous.

No input delay constraints exist for both these signals. Wrn is generated by external bus controller of a Microcontroller and the timing is not deterministic due to the MCU software behaviour.

wrn is driven LOW for 125 ns by the MCU and a 32 MHz FPGA clock should capture it without miss. Is Input delay still needed in this case?

SyafieqS
Moderator
259 Views

Hi Naveen,


"wrn and clearn are asynchronous"

Seem to me it is clock domain crossing.


You can refer to link below on how to constrain CDC.

https://www.intel.com/content/www/us/en/support/programmable/articles/000080400.html


But in general if this is CDC, you do not have a set_false_path constraint between the two clock domains, if you don't want paths between them to be analyzed for setup and hold then you can use set_clock_groups which has a lower precedence. This due to the skew across the bus can be more than 1 clock period which can cause functional errors.



SyafieqS
Moderator
246 Views

Naveen,


Are you able to constraint the asynchronous clock using the suggested constraint?


SyafieqS
Moderator
212 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 



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