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Update MAX10 CFM from Microcontroller using serial interface.

GD76
Novice
365 Views

After reading the Max10 user config document and looked at I2C RSU, not sure of this. The FPGA cannot have NIOS. The I2C based user logic described in User config need NIOS. My legacy boards has a microcontroller running C firmware and a FPGA.  However, the JTAG of the FPGA are not accessible for field upgrade directly. A serial SPI is available that connects the FPGA to the microcontroller. In legacy, the old FPGA bitstream (RBF file) is packaged together with firmware and programmed onto an external flash. The microcontroller through SPI updates the SRAM based FPGA. The FPGA is obsolete. Looking to upgrade that to Max10 FPGA. Looking for full app note and reference design that can walk me through using Max10. The microcontroller may update the FPGA's CRAM or the CFM. It is confusing reading through the dual configuration because it does not look similar to what I want to do. 

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4 Replies
YuanLi_S_Intel
Employee
346 Views

Yes, we can have NIOS II instantiated in MAX10. You may see the guide below:

https://www.intel.com/content/dam/altera-www/global/en_US/uploads/4/45/Hello_World_Lab_Manual_MAX10....


GD76
Novice
317 Views
YuanLi_S_Intel
Employee
307 Views
jozephka99
New Contributor II
268 Views

For UART i have this, you can translate into SPI:

community.intel.com/t5/Programmable-Devices/Discrete-RSU-User-Logic/m-p/1269878#M79509

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