Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21615 Discussions

Urgent: Different timing analysis result for DMA

Altera_Forum
Honored Contributor II
‎03-25-2011 03:13 PM
1,274 Views

Hello, I did a timing analysis for DMA to transfer 2MB of data. The first time i executed it, using DMA, the system improved by 88.75%. When I ran it for 2nd time, the performance became 48.5% only. why the performance will decrease from 88.75% to 48.5%? I did not change the code or the core.

0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎03-28-2011 07:18 AM
509 Views

Do you run it twice in a row from the same software, do you re-upload a new software between the two tests, or are you reconfiguring the FPGA and upload the software between the two tests? 

You should put some Signaltap probes on the DMA's master to see if anything different is happening during the tests.
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-28-2011 07:54 AM
509 Views

Yeah, it is correct now. I did a mistake by adding some function in DMA part. Thanks!

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.