Below is the OSI model:
The TSE IP or this example design is supporting the Physical Layer and Data link layer (MAC), which are layers 1 and 2 from the OSI model. This depends on what you are trying to achieve, and you might need to create other layers on your own to achieve that. Besides, you may consider using other tools on your PC (e.g. Wireshark) to monitor the ethernet packet transfer.
I can't find any examples for the Arria V GX board. Do you have a suggestion for which board to look at it?
I went through the Using Triple-Speed Ethernet Tutorial IP for DE2-115 Boards today. I modified it to work with the Arria V GX. I attempted to use the Monitor program but I can't get it to work. I suspect this is because the DE2-115 board has two Ethernet jacks that the NiosII c file uses for the test and the Arria V GX only has a single Ethernet jack.
I am still lost on how to send data from the FPGA to the PC and back. I think I have all the modules I need but I can't figure out how to interact with all the modules to do what I want.
This is the Triple-Speed Ethernet Tutorial I went through.
The simple socket driver example design is not available for the Arria V from the link below. Therefore, you might need to do the design migration from other devices manually.
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