Use shared pll with serdes without DPA or CDR?

[Altera_Forum]

Hello, 

 I am trying to transmit data via serial connection over the HSMC-Connector using LVDS between to boards (Cyclone IV and Cyclone V-SoC, obviously with different clock sources). Therefore I have on each side an altlvds-tx and an altlvds-rx megafunction. Does it thus make sense to connect the rx and tx pll on each side instead of clocking each receiver by its corresponding transmitter? Without DPA or CDA, I will run into phase shift problems when using shared pll for rx and tx, depending on synchronicity of the clock sources and cable length, am I right?   In which cases is it sensible to use shared pll (apart from my case where Quartus cannot place the matching fractional pll when using the HSMC-Connector...)?  I am asking this, as I would like to know if I should try further to use different clocks for rx and tx (and to solve the placing issue) or to investigate the possibility of inserting a synchronizing solution.  Thanks  herrhannes

[Altera_Forum]

If you can, I suggest sending the respective clocks with the data and clocking the data into the receiving device with that clock. Depending on the respective trace delays between data and clock you may require a PLL at each device's receiver to guarantee setup & hold on the data being clocked into the fabric. 

   --- Quote Start ---  Does it thus make sense to connect the rx and tx pll on each side instead of clocking each receiver by its corresponding transmitter?  --- Quote End ---    This implies you'd consider operating the LVDS rx & tx links from the same clock. You're going to have to cross clock domains somewhere. It may make sense to only do this a one end of the link, not both. It could be an acceptable way of operating the link, depending on your system requirements.

[Altera_Forum]

Thank you. That is exactly what I feared. So I would rather try to find a solution to my placement problem.