Using ALTLVDS_RX megacore

[Altera_Forum]

Hi there, 

  I would be really grateful if someone could shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, since it is in 12 bits and it is transmitted throught 2 wires (which means 1 channel? am i right), how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other.   Michael :confused:

[Altera_Forum]

720Mbps stream with using LVDS pair results in 720MHz frequency. Are You suere Your FPGA can handle this? 

 There are no *_P or *_N wires.. You will have only one wire and it will rename (or actually add) automatically to _P and _N wires in the assignment editor or pin planner.

[Altera_Forum]

It is a DDR stream, so the source clock is only 360MHz.

[Altera_Forum]

Then check docu about ALTDDIO

[Altera_Forum]

--- Quote Start ---  Then check docu about ALTDDIO  --- Quote End ---    I'm not sure what you mean. A DDR stream of X Hz clock rate has 2X bps. By consequence a DDR streem of Y bps has Y/2 Hz clock rate. It would have been nice if you could point to the relevant document and page(s) showing this doesn't hold.  So the 360 MHz input clock should be feasible with the faster speed grades (c6 , C7) of Cyclone II onwards. For Stratix II all speed grades will probably do.

[Altera_Forum]

All differential signaling should have 2 wires (but i am not sure about what's channel meant by the core settings), one plus and one minus. 

And yes, my LVDS is in DDR, so the frequency is only 360MHz.  Back to the original question, " how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other. "

[Altera_Forum]

Using ALTLVDS_RX: you could choose a factor of 6 and concatenate 2 6-bit readings to 12 bit. Maybe a bit tricky to align. 

Doing it yourself isn't that difficult (as you are aware of). You don't need the fancy DPA to interface to high-speed ADCs (like T.I. and A.D. and others offer).   In your logic module you just need to specify a single pin for each LVDS input/output-pair. The other (inverted) signal will be assigned by either the Assignment Editor or the Pin Planner, where you specify the applicable interface and voltage level. The positive pin will have the name you gave in the module definition, the other will get a'(n)' postfix to identify it as being the negative one of the pair.

[Altera_Forum]

If you are targetting to a Cyclone device, you should be able to type in a deserialization factor of 12 manually. Personally, I prefer a hand coded SERDES as sugested in this thread:  

http://www.alteraforum.com/forum/showthread.php?t=27121 It's very similar to what the altlvds IP does with software SERDES, but it's more straightforward with factors like 14 and phase/delay settings are much clearer in my opinion.

[Altera_Forum]

I could type in the deserialization factor manually in Quartus 2 Version 9.0 or 9.1, but it does not allow me to manually type in a custom factor in Quartus 2 10.0sp1 that i am currently using. 

 Is there any way to go around this? can i generate the verilog code with 10 bit deserialization factor first, and then manually change the defram within the verilog settings into 12 bits?