What is the processing speed limitation of Cyclone IV E with speed grade C7?

[Altera_Forum]

Hi everyone, 

 Does anyone know, what is the maximum processing speed of Cyclone IV E (with speed grade of C7) within the FPGA fabric?   Knowing that PLL on Cyclone IV E can generate up to 1.3 GHz, does it mean the FPGA fabric will process up to that speed too?  And where can i find out more on these information? I am trying to receive and process high speed LVDS data streams from a high speed and high resolution ADC for ultrasound application.   Thanks in advance!  Regards, Michael

[Altera_Forum]

You will need to perform your own register-to-register tests to determine what the maximum operating frequency is. 

 Processing frequencies of >150MHz should be possible.  Ultimately it will also depend on how much power you can afford to dissipate.  What speed LVDS did you need?  This board uses 125MHz LVDS on the front-panel connectors and 500MHz LVDS to interface to the 1GHz digitizers.  http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/) http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)  The digitizers test document has a discussion on the LVDS transceivers, along with scope captures, see p58 and on.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 The LVDS output from the ADC (TI's AFE5808) i am trying to receive, runs at 910 Mbps, and i am trying to deserialize the serial data from LVDS using DE2-115.   Since i know the speed limitation of DE2-115 (for HSMC) is 740MHz, so i am trying to multiplex the LVDS into 2 HSMC port. But i am not sure if this will work.  Any advice?   Regards, Michael

[Altera_Forum]

The Cyclone IV handbook indicates 875 Mbps Rx for LVDS. Where did 'the speed limitation of DE2-115 (for HSMC) is 740MHz' come from (lower speed grade part perhaps)? 

 If the data from the ADC is 910Mbps, then I assume you are running the AFE at 14-bits, 910Mbps/14-bits = 65Msps. You could try running the part in 12-bit mode, 12*65 = 780Mbps, or you can reduce the 65MHz clock to something that your tests can handle.  If you absolutely have to run the part at 910Mbps, then you will need to get an evaluation board with faster LVDS receivers.  Keep in mind that you first need to evaluate and understand parts before going off and designing a board, or applying the device in your final application. There should be nothing wrong with operating the AFE at a lower frequency initially to learn how to use the part.  Note that the TI TW3100 board has a Stratix II device on it. Perhaps that board has an adapter to interface to the AFE evaluation board.  http://focus.ti.com/docs/toolsw/folders/print/tsw3100evm.html  Ouch! $3499. Ok, so maybe not! The Terasic DE3 and DE4 boards would probably be a better bet then.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Yes, the speed grade for DE2-115 is C7, hence the LVDS receiver only goes up to 740MHz. (Table 1–36 (p466) of the latest Cyclone IV handbook), am i right?  I will first run the part with a lower frequency during the test. I know having a higher speed grade FPGA will probably fix all these speed issues, but i've already purchased the tPad(LCD + DE2-115)(costed me USD 850.00) for my senior design using my own money, so switching FPGA is probably not an option for me.  So back to my previous question. If i use 2 HSMC ports(all together 4 I/O) to receive the same LVDS signal, and my shift registers(14bits + 14bits) defined in verilog are running at half the speed of the LVDS signal. One group (14 bits) shift registers are triggered on the rising edge, while the other group (14 bits) shift registers are triggered on the falling edge. In another words, i want the 2 HSMC ports to catch the LVDS data stream in alternate turns, to overcome the speed limitation issues. Do you think this approach will work? if no, what do you think is the limiting factor?  Thanks professor!  Regards, Michael

[Altera_Forum]

Hi Michael, 

 Yes, the LVDS receiver is rated to 740Mbps (note: Mbps, not MHz).  So assuming you run the LVDS receiver in x7 mode, the data will enter the FPGA at ~105MHz. The ADC could be run at ~52MHz.  Unfortunately the scheme of using two LVDS receivers out-of-phase will not work. The issue will be that you cannot improve the setup/hold time of the receivers.   Adding an external clocked multiplexer would be a lot more trouble that its worth. I'd recommend starting out with the AFE operated at say 50MHz.  Would that be ok for your project?  Once you get the part operating at 50MHz, there is nothing to stop you from 'overclocking' your FPGA. You might be lucky and find that your board works fine at 910Mbps.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I've always wanted to ask what's the difference between MHz and Mbps in LVDS? Since LVDS is basically in binary, which is on and off per unit time, so i thought using MHz to describe Mbps here would be the same?  Could you elaborate a little more on how you get 105MHz?, and what is setup/hold time of the receivers?  "Adding an external clocked multiplexer..." i wanted to make this in the FPGA using verilog. If this does not work, do you think it will work if i use a discrete deserializer chip?  And how could one overclocks the FPGA? cool down the FPGA? increase core voltage? this is getting interesting!.  Thanks!  Regards, Michael

[Altera_Forum]

One usually uses "MHz" for clock frequencies and "Mbps" for data rates. 

In the case, the LVDS receiver uses DDR, so the data rate (per pin) is twice the clock frequency.

[Altera_Forum]

Hi Michael, 

   --- Quote Start ---   I've always wanted to ask what's the difference between MHz and Mbps in LVDS? Since LVDS is basically in binary, which is on and off per unit time, so i thought using MHz to describe Mbps here would be the same?   --- Quote End ---    There's often a factor of two between MHz and Mbps. Eg., look at connector specifications from Samtec (makers of HSMC connectors). They will specify connectors at eg. 9GHz or 18Gbps.  If I have a clock at say 100MHz, the fastest I can toggle a signal using the rising edge is 100Mbps. However, as the other poster commented, using both the rising and falling edges of the clock, you can get two bit toggles per time period, so 200Mbps, twice the clock frequency. In the case of the 740Mbps LVDS, the 'clock' is 370MHz DDR.    --- Quote Start ---   Could you elaborate a little more on how you get 105MHz?, and what is setup/hold time of the receivers?   --- Quote End ---  If your ADC is 14-bits at 50MHz, then the serialized data rate is 50*14 = 700Mbps. If you receive that via LVDS, with the receiver in x7 mode, then the data will be deserialized inside the FPGA as 7-bits every 100MHz. You would then need to wait for the next 7-bit sample from the LVDS receiver before you had the 14-bits you need for processing.  I'm not sure what the setup and hold time of the receivers is. Timequest will tell you. Create an LVDS design and perform a timing analysis.    --- Quote Start ---    "Adding an external clocked multiplexer..." i wanted to make this in the FPGA using verilog. If this does not work, do you think it will work if i use a discrete deserializer chip?   --- Quote End ---  Its not worth thinking about this route. The best solution is an FPGA. It just happens that you can't run your ADC at 65MHz. You haven't indicated that running it at 50MHz is a problem. Is it?    --- Quote Start ---    And how could one overclocks the FPGA? cool down the FPGA? increase core voltage? this is getting interesting!.   --- Quote End ---  Initially, you'd try to lie :) You compile the project for the highest speed grade device and see if the design meets timing. If it does, then you download it to your board and see if it works. If it doesn't, then, I guess, try changing the temperature. The other way to overclock is to control the clocks. The Altera ALTPLL megafunctions you use in the design will be automatically configured by your selections in GUIs. You can however, control all the PLL parameters directly using the ALTPLL_RECONFIG function, so you use that to increase the receiver frequency until things break.  Controlling the PLL phase is very useful. It allows you to slide the FPGA clock closer to the edges of the receiver eye patterns, and from that you can determine how much timing margin you have. Eg. you could determine whether 910Mbps is possible while running your design at 700Mbps.  How many channels of ADC do you need? Another scheme you may not have thought of, is to operate the ADCs out-of-phase by 180-degrees, eg. by using an inverted clock. I did not look at the device data sheet to see whether this was a feature, but perhaps you could use two ADCs per analog signal. Then you could interface to each ADC at 50MHz, yet be sampling the signal effectively at 100MHz. Inside your FPGA, you would take the 14-bit samples from each FPGA and interlace them to create the effective 100MHz ADC. That is the theory anyway, in practice you might have to initialize the system to get the clock phases and the channel gains correct. Depending on how many bits you really need, it might be ok.  What are you trying to do with the AFE? Ultrasonic beamforming for medical, NDT, sonar?  Cheers, Dave

[Altera_Forum]

Dave,  

 I just happens to see your latest post when i check back all my previous post, i am not sure why i didn't get a notification via email. Anyway, thanks for all these information, its very helpful.    --- Quote Start ---   What are you trying to do with the AFE? Ultrasonic beamforming for medical, NDT, sonar?  --- Quote End ---  This is our college senior design project, i am majoring in Electrical engineering in a bachelor degree, but our professor just choose an extremely challenging project for us, personally i haven't have much experience on FPGA, we only have 2 classes with CPLD. This AFE5808 from TI will be used on a pig's heart for researching in Shearwave Dispersion Ultrasound Vibrometry (SDUV) imaging.   I have a new question, and this is quite critical and urgent, i would be really grateful if someone shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, since it is in 12 bits and it is transmitted throught 2 wires (which means 1 channel? am i right), how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other.   Michael

[Altera_Forum]

Hi,  

IIRC, although the dropbox only shows "10", I think you can type in 12 to generate a altlvds_rx core with a deserialization factor of 12.  If that doesn't work out, you'll have to write out your own deserializer -- search this forum, I think there are code snippets arround.  In Verilog (or VHDL), you just use the "p" signal and let the tools automatically create the "_n" signal. That is, in your Verilog, you only need a "HSMC_RX_D" signal. When you assign that signal as LVDS, the fitter will automatically create a "HSMC_RX_D_n" signal.

[Altera_Forum]

Hi Michael, 

   --- Quote Start ---    I just happens to see your latest post when i check back all my previous post, i am not sure why i didn't get a notification via email. Anyway, thanks for all these information, its very helpful.   --- Quote End ---  Hopefully you'll read this reply :)    --- Quote Start ---    This is our college senior design project, i am majoring in Electrical engineering in a bachelor degree, but our professor just choose an extremely challenging project for us, personally i haven't have much experience on FPGA, we only have 2 classes with CPLD. This AFE5808 from TI will be used on a pig's heart for researching in Shearwave Dispersion Ultrasound Vibrometry (SDUV) imaging.   --- Quote End ---  Perhaps your professor gave you a hard project because he felt you were up to the challenge. Lets prove him right.    --- Quote Start ---     I have a new question, and this is quite critical and urgent, i would be really grateful if someone shed some light for me.... alright here's the scenario; A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, since it is in 12 bits and it is transmitted throught 2 wires (which means 1 channel? am i right), how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other.   --- Quote End ---  Your ADC will be sampling at 12-bits at 60MHz clock and then serializing the data to give you a 720Mbps serial data stream (which is within the 740Mbps LVDS limit of your FPGA). The altlvds_rx component can be configured for deserialization rates of 1 through 10. You can use any of these rates to capture your data, and then inside the FPGA you have to reconstruct the LVDS received bits to your ADC 12-bit data. The logical choice (minimum effort) given that demux-by-12 does not exist is to use demux-by-6. This means that internal to your FPGA, you will be getting 6-bits at 120MHz. You can write that to a dual-ported RAM, where the RAM is configured with one side written at 6-bits at 120MHz clock, and the other side read as 12-bits at 60MHz.  While in theory this sounds simple, it will be complicated by one fact. Where in the 720Mbps serial stream does the receiver start serial-to-parallel conversion of the data? If the receiver is not aligned to start 'unpacking' bits in the order the ADC 'packed' them, then you have a problem. The LVDS receivers operate with an external 'frame clock', where this frame clock is used to tell the receiver where a data frame starts and ends. In your case, since the 60MHz ADC serializes the 12-bits into a 720Mbps stream, the 60MHz clock is the frame clock, the question will be what is the timing of the 60MHz clock relative to the data. To understand what I am talking about, go and setup a modelsim simulation with; a fake ADC that serializes data to 720Mbps (eg., your simulation can write 12-bit data to dual ported RAM, that gets read at 6-bits, and then sent to an altlvds_tx channel), and then capture that data. You can put in delays on the frame clock and see how your received data gets messed up.  Even if your 60MHz data is aligned perfectly with your 12-bit ADC data, you'll have to work out how to pack your 6-bit data into the recovered ADC 12-bit samples. One way I can think of is that your 120MHz receive clock can use the 60MHz frame clock, eg., the 12-bit data will be 2 x 6-bits of data, and the first 6-bit value will occur when the frame clock is high, and the second when the frame clock is low (relative to the 120MHz receive clock). Actually, with this scheme, you would not use dual-ported RAM with different port widths to capture data, you'd just use a 12-bit receive register clocked at 120MHz; the frame clock would be used as a low/high 6-bit enable, and at every high clock (after a complete 12-bits was updated in the register), you would write to a 12-bit dual-clock FIFO. The FIFO would be clocked at 120MHz on one side, and be written every second clock with 12-bits, while the other side of the FIFO would be clocked at 60MHz and read every clock.  If the ADC has a test-pattern mode, then you can always consider using that to initialize the system.  Try to figure this out. If it gets too overwhelming, let me know, and if I have time, I can write an example in VHDL.  Cheers, Dave

[Altera_Forum]

Dave, 

   --- Quote Start ---   Even if your 60MHz data is aligned perfectly with your 12-bit ADC data, you'll have to work out how to pack your 6-bit data into the recovered ADC 12-bit samples. One way I can think of is that your 120MHz receive clock can use the 60MHz frame clock, eg., the 12-bit data will be 2 x 6-bits of data, and the first 6-bit value will occur when the frame clock is high, and the second when the frame clock is low (relative to the 120MHz receive clock). Actually, with this scheme, you would not use dual-ported RAM with different port widths to capture data, you'd just use a 12-bit receive register clocked at 120MHz; the frame clock would be used as a low/high 6-bit enable, and at every high clock (after a complete 12-bits was updated in the register), you would write to a 12-bit dual-clock FIFO. The FIFO would be clocked at 120MHz on one side, and be written every second clock with 12-bits, while the other side of the FIFO would be clocked at 60MHz and read every clock.   --- Quote End ---    My eyes just went numb from this point, anyway. Thank you very much, this is very helpful. I will try my best to understand it, and if i get stuck again, i will post some questions here.   Thanks!   Michael

[Altera_Forum]

Hi Michael, 

   --- Quote Start ---   My eyes just went numb from this point   --- Quote End ---  Ha!  A picture is worth a thousand words ...   http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)  p64: the top trace is the 'frame clock' the bottom is serialized data.  p71 and on explain the receiver deserializer and framing.  Try to redraw the figures on p73 and 74 for your case. For example, for every period of your 60MHz frame clock, you diagrams would have 12-bits of serialized data. However, since the LVDS receiver would be configured in 6-bit mode, you would get a parallel output word every half frame clock (my diagrams don't show the parallel data inside the FPGA, but yours could).  Once you can draw a figure, your eyes will become less numb :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi Michael,  Ha!  A picture is worth a thousand words ...   http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)  p64: the top trace is the 'frame clock' the bottom is serialized data.  p71 and on explain the receiver deserializer and framing.  Try to redraw the figures on p73 and 74 for your case. For example, for every period of your 60MHz frame clock, you diagrams would have 12-bits of serialized data. However, since the LVDS receiver would be configured in 6-bit mode, you would get a parallel output word every half frame clock (my diagrams don't show the parallel data inside the FPGA, but yours could).  Once you can draw a figure, your eyes will become less numb :)  Cheers, Dave  --- Quote End ---     Wow.... that CARMA board is really impressive.. you just gave me a thousand more words to read. I will try to read your material as my main reading material for the rest of my summer holiday, and hope to understand maybe 20-40 % of it.   Thanks for your help, i really appreciate it.:-P   Michael

[Altera_Forum]

--- Quote Start ---   Wow.... that CARMA board is really impressive..   --- Quote End ---  Thanks :)    --- Quote Start ---   I will try to read your material as my main reading material for the rest of my summer holiday, and hope to understand maybe 20-40 % of it.   --- Quote End ---  Make sure to both read and write some code. If you can understand how to create a simulation that generates and captures your serial data, you will have a good chance of getting it working in hardware. Don't forget that with a loopback from TX-to-RX your 'simulation' can also be tested in hardware.    --- Quote Start ---   Thanks for your help, i really appreciate it.:-P   --- Quote End ---  No problem! Keep asking questions. Welcome to engineering, its a lot of fun!  Cheers, Dave