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HY68
Beginner
459 Views

Using DDIO_In to read ADC data and timing analysis

Hi,

I'm trying to use DDIO to capture ADC LVDS data from ADC3224. The device is set at 2 wires(x6) mode. The FPGA is Arria10(10AX027) and running at 100MHz sampling rate, which makes the ADC_FCLK and ADC_DCLK equal to 100 and 300MHz.

In the debugging process, I've read following application notes:

1.     Intel AN433, Arria10 GPIO user guide and Timing Analyzer Cookbook,

2.     TI, "Interfacing Altera FPGAs to ADS4249 and DAC3482"

3.     "Source-Synchronous Timing with TimeQuest", written by Ryan Scoville.

This project is built under Quartus Prime Pro 17.1.2 and have been tested in different devices and environments as below:

1.      Arria10, GX027/ GX066, Quartus Prime Pro 17.1/18.1/19.1/19.2

2.      Cyclone 10 GX, Quartus Prime Pro 17.1/18.1/19.1/19.2

However, there’s no noticeable timing difference between these combination.

The ADC output data ADC3224_DA[0] and ADC3224_DA[1] are connected directly to DDIO_In IP-core, which is clocked by ADC_DCLK without IOPLL. According to ADC3224 datasheet, ADC3224_DA[1:0] and ADC_DCLK are center-aligned, hence in SDC I can constraint the clocks as below:

#**************************************************************   # Create Clock   #**************************************************************   #FCLK=100MHz   create_clock -name {ADC_DCLK_Input} -period 3.333 -waveform { 0.833 2.5 } [get_ports {ADC3224_DCLK_In}]   create_clock -name {ADC_VirtualClk} -period 3.333   create_clock -name {B3A_RefClk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {B3A_RefClk}]   create_clock -name {ADC_FCLK_Input} -period 10.000 -waveform { 0.000 5.000 } [get_ports {ADC3224_FCLK_In}]       #**************************************************************   # Create Generated Clock   #**************************************************************   derive_pll_clocks   derive_clock_uncertainty   #**************************************************************   # Set Input Delay   #**************************************************************   # set input constraint using setup and hold wrt virtual clock   # if device datasheet provides Tsu and Th only:   # max = Tperiod/4 - Tsu   # min = Th - Tperiod/4   set_input_delay -clock { ADC_VirtualClk } -max 0.153 ADC3224_DA0   set_input_delay -clock { ADC_VirtualClk } -min -0.063 ADC3224_DA0   set_input_delay -clock { ADC_VirtualClk } -clock_fall -max -add_delay 0.153 ADC3224_DA0   set_input_delay -clock { ADC_VirtualClk } -clock_fall -min -add_delay -0.063 ADC3224_DA0       set_input_delay -clock { ADC_VirtualClk } -max 0.153 ADC3224_DA1   set_input_delay -clock { ADC_VirtualClk } -min -0.063 ADC3224_DA1   set_input_delay -clock { ADC_VirtualClk } -clock_fall -max -add_delay 0.153 ADC3224_DA1   set_input_delay -clock { ADC_VirtualClk } -clock_fall -min -add_delay -0.063 ADC3224_DA1   #**************************************************************   # Set False Path   #**************************************************************   set_false_path -setup -rise_from {ADC_VirtualClk} -fall_to {ADC_DCLK_Input}   set_false_path -setup -fall_from {ADC_VirtualClk} -rise_to {ADC_DCLK_Input}   set_false_path -hold -rise_from {ADC_VirtualClk} -rise_to {ADC_DCLK_Input}   set_false_path -hold -fall_from {ADC_VirtualClk} -fall_to {ADC_DCLK_Input}

 

The input delay value is based on ADC3224’s Tsu and Th, and I’m trying to use same-edge capture (virtual clock à ADC_DCLK) instead of opposite-edge.

After all these setting and timing constraint, I got setup time violation shown as figure “step_violate_DA0”. What makes me confused is in the input data path, why the “DDIOIN_X150_Y16_N52” internal connection spent so much time (7.688ns) and when I click to view this path in “Resource Property Viewer”, it surprises me that looks like the fitter didn’t locate this path into DDIO_In block (right-down region of figure “DA0_Input_Path”). It happens on every device and Quartus version I’ve tried above. What makes me confused is even though there’s time violation, but in SignalTapII, the ADC data are correct.

In my understanding, SDC timing constraint will instruct the fitter to place logic blocks and adding routing delay as much as it could to match setup and hold time. The case I met is more like the fitter got wrong instruction and trying to adding extra data path delay in internal connection.

Furthermore, if data path delay in “DDIOIN_X150_Y16_N52” can’t be avoid, according to TimeQuest’s waveform, should I add multi-cycle path constraint to specify the offset of latch edge?

If I got any misunderstanding of timing constraint, please kindly notice me, thanks.

step_violate_DA0.JPGDA0_Input_Path.JPG

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9 Replies
63 Views

Hi,

 

According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf (Page 40), you have to create the virtual clock with the same period and phase shift as the real clock in the source device, which means that the following two constraints need to have same phase shift.

 

create_clock -name {ADC_DCLK_Input} -period 3.333 -waveform { 0.833 2.5 } [get_ports {ADC3224_DCLK_In}]

create_clock -name {ADC_VirtualClk} -period 3.333

 

Thanks.

HY68
Beginner
63 Views

Hi YY,

Thanks for reply. In my understanding and according to ADC3224 data sheet(page 45), data are clocked out 90 degrees prior the rising and falling edge of DCLK.

Waveform below is the output timing diagram of ADC3224 in x6 mode, and the green signal is the virtual clock I added to described the clock of ADC output registers.

ADC3224_x6_virtual.JPG

In my application, Frame Clock(FCLK) runs at 100MHz and therefore both virtual and actual output clock of ADC are set as 300MHz in SDC.

Therefore I think it's more like the definition "Case 2: The FPGA is the receiver and does not phase-shift the clock" in Ryan Scoviller's writing, "Source-Synchronous Timing with TimeQuest".

That's why in my SDC I described a 90 degrees(0.833 ns) phase shift on ADC_DCLK_Input, instead of making ADC_DCLK_Input and ADC_VirtualClk having the same phase shift.

Should I have any misunderstanding, please let me know.

Thanks,

 

63 Views

Hi,

 

May I request a sample test case for investigation?

 

Thanks.

HY68
Beginner
63 Views

Hi YY, Of course, attached is the whole archived project. The QP I'm using is 17.1.1 Build 273 Thanks! Intel Forums <supportreplies@intel.com> 於 2019年8月25日 週日 下午10:53寫道:
HY68
Beginner
63 Views

add project file.

63 Views

Hi,

 

I am still working on it. Please allow me some time on this.

 

Thanks.

HY68
Beginner
63 Views

Hi YY,

No rush, appreciate for your support.

 

63 Views

Hi,

 

I checked in the Timing Analyzer. The register is located within the I/O. According to the user guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf, you may set the delay elements manually in the Intel Quartus Prime settings file (.qsf). 

 

Input Delay Element

set_intance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63>

 

Output Delay Element set_intance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15>

 

Output Enable Delay Element

set_intance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15>

 

You may try to set the max and min value and see if it helps the timing.

 

Thanks.

 

63 Views

Hi,

 

May I know if you have any updates?

 

Thanks.