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I'm looking for examples of using the dynamic reconfiguration of the GXB's in Stratix II GX to switch from 2.5Gbps PCIe 1.0 mode to 5.0Gbps PCIe 2.0 mode. Has anyone done this and are you willing to share example code? So far I generated MIF files for the two modes and I wrote an FSM to load the MIF files, but it isn't working yet. SignalTap shows me that the MIFs for each channel are loading, but the PCIe will not train. Note: It trains fine if I just load the SOF, so the MIFs should be good.
Thanks, CraigLink Copied
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Hi,
I'm adding a message to ask if someone could put an schema of the signals we have to connect, especially the clocks, to the alt2gxb. Does the alt2gxb work without any digital/analog reset as it's suggested in the minimal version of it? In exchange of some info I can lead someone who needs into the entire process of coding a complete PCIe IP (I've done a 1x and 4x) and I can help with the XIO1100. Thanks Marc- Mark as New
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hi,
so alt2gxb does need a reset sequence. the reset sequence is given in the stratix 2 handbook- Mark as New
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Hi ckeefer,
I would like to build my own PCIe gen2 Phy for a Stratix II GX but I'm not making much progress with the alt2gxb configuration. Altera just seems to supports gen 1 within the configurator, but you wrote that you have a solution for gen2 that trains the link. Can you or anyone here give some hints how to configure the alt2gxb to support gen2 ? Thanks Martin
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