Hi,I want to use an external LVDS Clock on the DE0-Nano-SOC. In the cyclone II , I select LVDS for pin planner and used a pll on the way of it. but this way do not work for DE0-Nano-SOC(My PLL Do not lock). How can i fix it? I used a 100 ohm resistor in the termination of LVDS pins.
You mention Cyclone II. DE0-Nano-SOC is a Cyclone V based board...Are you happy with your LVDS signal at the FPGA's pins? Have you looked at it with an oscilloscope? Does it work if you take the PLL out of your design? Can you use your LVDS clock to operate some logic directly? If the PLL doesn't lock it suggests your LVDS clock is out of spec for the PLL. Cheers, Alex