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Altera_Forum
Honored Contributor I
1,292 Views

error : Cyclone V XCVR Illegal constraint of Channel PLL

Hi All, 

 

As you can see the attachement "xcvr_pin_planner", I'm using 4 transceivers in the cyclcone V ST FPGA. 

I use only one "Transceiver reconfiguration controller" configured for 8 reconfiguration interfaces (grouping option = 2,2,2,2). 

 

With this configuration i have this error (with quartus 14.1 and 15.1) : 

 

Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)) Error (175020): Illegal constraint of Channel PLL that is part of Cyclone V Transceiver Native PHY altera_xcvr_native_av to the region (0, 40) to (0, 42): no valid locations in region Info (175028): The Channel PLL name(s): sFPDP_CONTROLLER:inst_sfpdp_controller4|sFPDP_XCVR:CMP_sFPDP_XCVR|sFPDP_PHY:CMP_sFPDP_PHY|altera_xcvr_native_av:sfpdp_phy_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas.rx_pma.rx_cdr Info (175015): The I/O pad iSFPDP_XCVR_RX3 is constrained to the location PIN_L2 due to: User Location Constraints (PIN_L2) Info (14709): The constrained I/O pad is contained within a pin, which is contained within a Receiver channel, which contains this Channel PLL Error (178014): Partition assignments may be preventing transceiver placement - transceivers optimizations across partitions are not supported in this version of the Quartus II software. For more information, refer to the Release Notes.  

 

If i remove CH1 (see attachement), I no longer have this problem
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2 Replies
Altera_Forum
Honored Contributor I
477 Views

The error message says "iSFPDP_XCVR_RX3 is constrained to the location PIN_L2", but from your pin planner shot it looks like pin L2 belongs to channel 1. So it makes sense that the error goes away when you remove channel 1. Better re-check your pin assignments for channel 3.

Altera_Forum
Honored Contributor I
477 Views

Hi, 

 

The pin assignement is good. i resolved the problem by Merging TX PLLs In Multiple Transceiver PHY Instances with Quartus Prime.
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