Honored Contributor II
04-20-2018 05:27 PM
I am looking into implementing a NIOS II on a Stratix 5 that is currently using CvP, and I have running into 2 issues which may be related to each other.Is there a way for the JTAG UART IP to be implemented within the core, not within the peripheral portion of the FPGA? When I disable the JTAG UART, the synthesis errors out on the fact that my NIOS II is not instatiated in the Top partition, since I don't have a full license. Is it possible to use a NIOS within the core of a CvP design? Thanks.