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Altera_Forum

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02-24-2016
06:44 PM

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Using a CARRY_SUM primitive for a TDC

Hi,

I've been trying for a few days now to use the CARRY_SUM primitive to implement a delay line TDC. I am designing a circuit that looks something like this: input -> CARRY_SUM -> DFF However, during MAP the carry buffers are all ignored. I think the logic is okay, because if I replace the CARRY_SUM with the LCELL primitive, I get the circuit I wanted. So I'm a little confused about the CARRY_SUM being ignored. I searched through the forums, and quite a few people ran into the same problem, but there wasn't a solution. Any ideas? Billy
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Sorry for the significant delay but I am trying to develop a delayline for a TDC. Once I have the delay steps I am happy to work with it. It seems that, no matter what I do I end up with even LAB steps (~500ps) of misaligned delays. Can you point me to some simple code for creating the delay taps required. DNL is not an issue so the simplest code will suffice. Thanks in advance.

SBuck4

Beginner

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07-30-2019
02:37 PM

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