Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Using cyclone iv E device as clock source

Altera_Forum
Honored Contributor II
‎11-11-2015 09:15 AM
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i wonder if it's realistic to implement a low-jitter( <10 ps ) differential (LVDS, LVPECL, etc.)clock source with the EP4CE6 FPGA.

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Altera_Forum
Honored Contributor II
‎11-11-2015 05:55 PM
386 Views

Check the handbook. It will have jitter specs for the PLLs. My guess would be no, you can't.

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