Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

Using megafunction vs just Verilog expression

Altera_Forum
Honored Contributor II
1,484 Views

What is the advantage of creating for exapple a multiplier with the megafunction wizard for multiplying m and n, vs just writing m*n?

0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
570 Views

I guess the megafunction would be the most optimised code, having the choice of pipelining. You can open the .v file and see what optimisations they implement. I guess that a MF multiplier would also take care of some exceptional cases such as multiplying infinity and such.  

 

Hope this makes sense
0 Kudos
Altera_Forum
Honored Contributor II
570 Views

A HDL multiply expression basically infers the same MegaFunction IP. But you don't have some of the options to control e.g. pipeling. For multipliers, the default is mostly O.K., so you don't need it.

0 Kudos
Altera_Forum
Honored Contributor II
570 Views

if you're using multipliers wider than 18 bits you'll want to use the Megafunction and add some pipelining if fmax is of concern.

0 Kudos
Reply