Reordering Data

[Altera_Forum]

Hi All, 

I'm at an early stage in a new project - I have a data stream from multiple sensors arriving into my FPGA and I want to re-order the data over a certain number of words before re-transmitting the data. Each frame of data is made up of 9600 words of data (16bits / point) arriving at about 60Msps. So I need a frame buffer to store each word as it arrives in it's new position in the frame until the frame is filled before re-transmitting. Since the data stream is continuous, I need two of these frame buffers or one of twice the overall frame size so that I can continue to receive and re-order a new frame while transmitting the previous (dual port?).   The frame buffer needs to be addressable like an array or (dual port) memory to enable the incoming words to be placed in the correct position before being read out.    Looking at the Cyclone III datasheet I can see that M9K blocks are very versatile and can be configured as various ways via the wizard.   Any advice anyone? Thanking you in advance

[Altera_Forum]

Your plan is ok. This is commonly done with data interleaving. 

You write continuously(address goes up regularly) into one of two memories. you read from the other memory as per reordering address. You need some care at switching between the two pipes.   think of your switch as two states: write to mem1, read mem2 write to mem2, read mem1

[Altera_Forum]

Thanks for the reply.  

 In relation to the amount of memory required and the speed of 80Msamples/sec do you have any feelings on the implementation? i.e. whether from pure VHDL code or accessing the FPGA's memory blocks via the wizard and interfacing to them.   Thanks again.

[Altera_Forum]

80MHz should be quite easy to achieve in most modern fpgas(logic part or mem blocks)