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Using tristate bridge with de0 nano (cyclone IVe

Altera_Forum
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Hello,  

I try since a couple of days to get cs, read and write signal on outputs of my de0 nano board. 

The goal is to drive a motor controller (LM628) which needs ck 8Mhz, cd, rd ,wr and a 8 bits data bus 

For the ck it's ok. I use a altpll function under Quartus. 

For the other signal I have created under Qsys: 

Clock source (50Mhz) 

Nios2/e processor 

Generic Tristate controller 

Tristate Conduit Bridge 

I take care of the links between each block. 

They have all the same clock. No error message during generation. 

Under Eclipse I write a small loop which make a write then a read on GENERIC_TRISTATE_CONTROLLER_0_BASE 

Then I run the program ... but nothing on outputs! cs stay at 3V3. 

Someone has an idea on this problem?  

I see a note (2011) that we have to put a Tristate conduit Pin sharer on some kind of Cyclone. I tried but no change. 

 

Thank you per advance for your help 

 

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