- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
If I have single ended CLK inputs 3.3V LVTTL in bank3a, b or 8a, b does it matter what voltage is applied to VCC_CLKIN.
I guess it only matters if one of those bank is using a differential input clock, when the pin must be set to 2.5v
Link Copied
5 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The threshold at which a clock edge is detected will be derived from VCC_CLKIN. So generally it will matter. However, in your case it shouldn't.
Cheers,
Alex
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks Alex..
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
The VCC_CLKIN is only used for bank 3 and 8 remaining not.Kindly find the page no:4 for the below document.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf
For other banks no need to consider
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I have 3.3v LVTTL clock signals on bank 3a, 3b and 8a, but differential clock input on 8b. So I will put 2.5V on Vcc_clkin8b but 3.3V on the others. Is this correct?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes others places which ever IO standard supports

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page