VCCIO and IO_STANDARD setting

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

VCCIO and IO_STANDARD setting

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Hi, I have a question regarding mismatch of VCCIO (on board voltage setting) and IO_STANDARD(Quartus setting): if the VCCIO connected to 3.3 V and for that particular IO bank, I specify 1.8 V LVCMOS IO standard in Quartus, will it cause problem if this IO bank need to drive both 3.3V and 1.8V signals? Does the IO_STANDARD setting in Quartus has to be matched with VCCIO pin voltage?

Thanks in advance!

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