VCCIO and IO standard difference

[Altera_Forum]

hi, 

I have cyclone IV GX Device, VCCIO of the bank is 3.3V. However, in Quartus project there 2.5V standard as input and output setting. There is basicly 4 signals in that bank, 2 inputs and 2 outputs. Inputs have the same voltage level than the VCCIO. So, basicly the only issue is that the Quartus settings is different than the used actual IO-voltage.  Is this a problem ? Of course it would be better to fix this, but it might be too late.  The signals are NOT time critical in any way at all. There is bascially NO current drawn from IOs either.  The design works also.  So, basically the only worry is will the FPGA be damaged ?  Tero

[Altera_Forum]

So, basicly the question is where does the  

IO standard has an effect in terms of  -output pin -input pin ?  -Tero

[Altera_Forum]

--- Quote Start ---  So, basicly the question is where does the  IO standard has an effect in terms of  -output pin -input pin ?  -Tero  --- Quote End ---    Hi Tero:  With the incorrect IO setting in quartus, the timing analyzer will not have the correct settings for the bank, and so your timing reports will be off. Also other cross checks will not be performed correctly (Like sso, input clamp warnings etc)  Pete

[Altera_Forum]

Hi, 

Thanks for the answer.  So, the FPGA wouldn't brake down because of this ?  Those things mentioned (sso, timing etc..) aren not that critical since signals are really almost static and they don't drive much current either. Only thing I am worried is the braking of the FPGA..  -Tero

[Altera_Forum]

Hi Tero.  

 The setting change on it's own won't break the FPGA, but overshoot on 3.3 data lines may. It's recommended clamp diodes are used in most cases.  I would just fix the Quartus project and recompile. If it's happy with 3.3 then you are all good and have no worries.  (Sorry for the late reply, I just saw your response today.)  Pete