Hi everybody,
In my project I have a FPGA module which reads inputs from INPUT_RAM and stores outputs in OUTPUT_RAM (both rams are altsyncram memories).
Inputs are computed in a Linux application running on the HPS and this application needs outputs produced by the FPGA module.
So the dataflow should be something like this:
1) HPS computes inputs
2) inputs are transferred from hps to input_ram 3) FPGA module computes outputs and stores them in OUTPUT_RAM
3) outputs are transferred from output_ram to hps 4) HPS uses outputs for its purposes
I've successfully managed to map INPUT_RAM and OUTPUT_RAM as Avalon MM slaves in the HPS memory space (with mmap()...) but this approach is too slow.
I think I should use the f2h_sdram interface to transfer data with a SGDMA or a mSGDMA controller, am I right?
Can someone give me a easy explanation about this possibility?
Thank you in advance!
