VERILOG LCELL Simulation

Altera_Forum · ‎11-11-2014

I have implemented a ring oscillator using LCELLs. I am able to simulate it using ModelSim-Altera with the following VHDL statement:

ring: for k in 0 to NUM_LUTS-1 generate

begin

inst_lcell : LCELL

port map(a_in => lut_ring(k),

a_out => lut_ring(k+1)

);

end generate;

lut_ring(0) <= lut_ring(NUM_LUTS-1) xor not(constq) after 1.702ns;

Simulation shows an oscillating output.

I have written the same code in Verilog.

genvar i;

generate for (i=0; i<NUM_LUTS-1; i++)

begin : lut_ring

// ALTERA BUG: LCELL must be lowercase for simulator

lcell lcell_inst (

.in ( lut_wire[i] ),

.out ( lut_wire[i+1] )

);

assign lut_wire[0] = lut_wire[NUM_LUTS-1] ^ ~constant;

How do you simulate it? If I put a# 1.702 after the ASSIGN it doesn't work! If you put# 1.702 before the

ASSIGN you get an error.

Thanks.

Altera_Forum · ‎11-12-2014

After a few hours of searching, reading and experimenting I finally found out how to simulate it. It's not the way it should be but it works! Verilog is more troublesome to simulate than VHDL. Oh well, the way it is.

Thanks anyway.