Weird half-word swapping with SRAM @ Generic Tri-State Controller

[Altera_Forum]

Hi, 

 I am experiencing this weird behavior with the Tri-State Controller connected to an SRAM: When I do a master_read_32 via the system console, both half-words are swapped! Single-byte reads or even individual half-word reads are fine (and in little endian order as I expected). Writing with master_write_32 is fine as well!  

• I am using the Generic Tri-State Controller and the Tri-State Conduit Bridge  
• The device's address width is 17bits  
• The Device's data width is 16bits  
• The Address width in The Tri-State Controller is thus set to 18 with a bytenable width of 2 as well as 2 bytes per word.  
• I am discarding the LSB of the byte address that I get out of the conduit by not hooking it up to the SRAM at all.  

   This thing doesn't make sense to me at all. I can read and write to my onchip memory on the same bus without problems. This is my first take with that component, so I might be overlooking something. Anyone has a clue what it might be?  Cheers, Peter

[Altera_Forum]

OK, 

 never mind... I recreated the project once again with the same paramters, and I can read and write the SRAM from the system console. Could have been a typo...  I discovered that it doesn't matter if I enter 2 or 4 in the bytes per word field. This field isn't documented either, can anyone clarify what I should enter there?  Cheers, Peter