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Altera_Forum
Honored Contributor I
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[VHDL] Compilation Order

Hi All, 

 

How can I define a compilation order of VHDL files in Quartus Prime? Can I do so by a *.do file? 

 

Thank you!
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8 Replies
Altera_Forum
Honored Contributor I
352 Views

it will compile them in the order they appear in the .qsf file. 

You can change the order in assignments -> settings -> files 

Or add a group of files via a .qip file (a .qip file is really just a tcl file)
Altera_Forum
Honored Contributor I
352 Views

 

--- Quote Start ---  

it will compile them in the order they appear in the .qsf file. 

You can change the order in assignments -> settings -> files 

Or add a group of files via a .qip file (a .qip file is really just a tcl file) 

--- Quote End ---  

 

 

I don't think this is completely right: The compiler will start with the top-level VHDL and infer from there on; it only needs to know where the childeren are. IMO the only order to observe is the one of the .sdc files, in the case of one of the .sdc needing info of a higher level one.
Altera_Forum
Honored Contributor I
352 Views

 

--- Quote Start ---  

I don't think this is completely right: The compiler will start with the top-level VHDL and infer from there on; it only needs to know where the childeren are. IMO the only order to observe is the one of the .sdc files, in the case of one of the .sdc needing info of a higher level one. 

--- Quote End ---  

 

 

The VHDL compiler needs an order, as packages will need to be compiled before entities etc. And if you use direct instantiation, you need the entity you are instantiating compiled before you instantiate it, otherwise the compiler throws an error. 

You may be getting confused between compilation and mapping. If you use component declarations, then you are pretty much free to compile the files in whatever order you want and it is the mapping stage (after compilation/elaboration) that will map entities on to components.  

 

I dont like using components because you have to essentially maintain the same code twice or more (once for the entity, once for the component). You also have to wait until elaboration finishes to find a mapping error. With direct instantiation it is the compiler that does the work, so it is much quicker to find errors, but compile order becomes important.
Altera_Forum
Honored Contributor I
352 Views

 

--- Quote Start ---  

The VHDL compiler needs an order, as packages will need to be compiled before entities etc. And if you use direct instantiation, you need the entity you are instantiating compiled before you instantiate it, otherwise the compiler throws an error. 

You may be getting confused between compilation and mapping. If you use component declarations, then you are pretty much free to compile the files in whatever order you want and it is the mapping stage (after compilation/elaboration) that will map entities on to components.  

 

I dont like using components because you have to essentially maintain the same code twice or more (once for the entity, once for the component). You also have to wait until elaboration finishes to find a mapping error. With direct instantiation it is the compiler that does the work, so it is much quicker to find errors, but compile order becomes important. 

--- Quote End ---  

 

 

I still beg to differ: I just re-arranged an old project into using a mix of entity.work and component declarations. 

This is the output of the analysis and synthesis step: 

Info (12021): Found 2 design units, including 0 entities, in source file ops2/ops2_types.vhd Info (12021): Found 2 design units, including 1 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/combmuxs/combmuxs.vhd Info (12021): Found 2 design units, including 1 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/combmux/combmux.vhd Info (12021): Found 2 design units, including 1 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/regmux/regmux.vhd Info (12021): Found 2 design units, including 1 entities, in source file reg2/reg2.vhd Info (12021): Found 2 design units, including 0 entities, in source file /qdesigns/bv5fpga/c-cam/bb/vhdl_packages/cc_data_types.vhd Info (12021): Found 2 design units, including 1 entities, in source file id2/id2.vhd Info (12021): Found 2 design units, including 1 entities, in source file pc2/pc2.vhd Info (12021): Found 8 design units, including 4 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/wide_logic/wide_logic.vhd Info (12021): Found 2 design units, including 1 entities, in source file alu2/alu2.vhd Info (12021): Found 2 design units, including 1 entities, in source file reg2/indexreg/indexreg.vhd Info (12021): Found 2 design units, including 1 entities, in source file ops2/ops2.vhd Info (12127): Elaborating entity "ops2" for the top level hierarchy Info (12128): Elaborating entity "id2" for hierarchy "id2:ids" Info (12128): Elaborating entity "combmux" for hierarchy "id2:ids|combmux:aludmux" Info (12128): Elaborating entity "pc2" for hierarchy "pc2:p" Info (12128): Elaborating entity "altsyncram" for hierarchy "pc2:p|altsyncram:instructionmemory" Info (12130): Elaborated megafunction instantiation "pc2:p|altsyncram:instructionmemory" Info (12133): Instantiated megafunction "pc2:p|altsyncram:instructionmemory" with the following parameter: Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5rq3.tdf Info (12128): Elaborating entity "altsyncram_5rq3" for hierarchy "pc2:p|altsyncram:instructionmemory|altsyncram_5rq3:auto_generated" Info (12128): Elaborating entity "reg2" for hierarchy "reg2:regio" Info (12128): Elaborating entity "indexreg" for hierarchy "reg2:regio|indexreg:x" Info (12128): Elaborating entity "altsyncram" for hierarchy "reg2:regio|altsyncram:regmemory" Info (12130): Elaborated megafunction instantiation "reg2:regio|altsyncram:regmemory" Info (12133): Instantiated megafunction "reg2:regio|altsyncram:regmemory" with the following parameter: Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ouq3.tdf Info (12128): Elaborating entity "altsyncram_ouq3" for hierarchy "reg2:regio|altsyncram:regmemory|altsyncram_ouq3:auto_generated" Info (12128): Elaborating entity "alu2" for hierarchy "alu2:a" Info (12128): Elaborating entity "LPM_ADD_SUB" for hierarchy "alu2:a|LPM_ADD_SUB:addsub" Info (12130): Elaborated megafunction instantiation "alu2:a|LPM_ADD_SUB:addsub" Info (12133): Instantiated megafunction "alu2:a|LPM_ADD_SUB:addsub" with the following parameter: Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_d8h.tdf Info (12128): Elaborating entity "add_sub_d8h" for hierarchy "alu2:a|LPM_ADD_SUB:addsub|add_sub_d8h:auto_generated" Info (12128): Elaborating entity "wide_and" for hierarchy "alu2:a|wide_and:wand" Info (12128): Elaborating entity "wide_or" for hierarchy "alu2:a|wide_or:wor" Info (12128): Elaborating entity "wide_xor" for hierarchy "alu2:a|wide_xor:wxor" Info (12128): Elaborating entity "combmux" for hierarchy "alu2:a|combmux:logresultmux" Info (12128): Elaborating entity "regmux" for hierarchy "regmux:iomux" Info (12128): Elaborating entity "combmux" for hierarchy "combmux:imux"  

 

The first 12 lines represent the order in the Assignments->Settings->Files. 

And the following lines show the order of elaboration ...
Altera_Forum
Honored Contributor I
352 Views

My version of ModelSim looks at compilation statement order. Tomorrow's version may change. My Quartus version does not care about order but it checks database to pick up called modules, tomorrow it may change. No fixed rules for these tools.

Altera_Forum
Honored Contributor I
352 Views

 

--- Quote Start ---  

My version of ModelSim looks at compilation statement order. Tomorrow's version may change. My Quartus version does not care about order but it checks database to pick up called modules, tomorrow it may change. No fixed rules for these tools. 

--- Quote End ---  

 

 

I realize there will/may be a difference between Quartus and ModelSim. I restricted myself to Quartus, although the OP might have ModelSim in mind and I failed to see that.
Altera_Forum
Honored Contributor I
352 Views

 

--- Quote Start ---  

My version of ModelSim looks at compilation statement order. Tomorrow's version may change. My Quartus version does not care about order but it checks database to pick up called modules, tomorrow it may change. No fixed rules for these tools. 

--- Quote End ---  

 

 

You have to be careful, as modelsim can pick up old versions if they exist in libraries already too.  

If you use a fresh build (clean database) for Quartus or Modelsim, then compile order is important.
Altera_Forum
Honored Contributor I
352 Views

As the original question in post# 1 is referring to Quartus Prime, I presume it's about Quartus rather than Modelsim compilation order. As for the former case I agree with Josyb. I have never observed a specific order in Quartus projects, with or without component declaration. Thus I'm under the impression, that Quartus is able to choose the compilation order (if necessary at all) automatically. (It does fine also for a clean build). 

 

Clearly different to Modelsim where instantiated components must me compiled first.
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