VHDL Modules for testbench - external Hardware

[Altera_Forum]

Hi, 

while setting up my testbech(es) for my electronics I'm now trying to implement the external devices to implement the response of these in real hardware to the FPGA code. While this might be easy to do for simple devices, the effort (and thus the possibility to make failures) increase with more complex devices. Additionally the intention is to check my code rather writing both "sides". Thus it would be best to have the VHDL module representing the external IC by the IC's manufacturer to be sure that the simulation does not suffer from self-made issues caused by mistakes in the external IC representing code. Do I need to contact all device manufacturers to ask for these VHDL modules (hoping they have these and provide them) or does a kind of central database for verification & validation support exist?  Kind regards

[Altera_Forum]

You will need to contact the manufacturers. SOme provide them on their websites, while some do not. Some probably dont even have the simulation models. 

Be prepared for models in Verilog, as thats what most of the models I have seen coded in. So if you have your code in VHDL, you will need a mixed code simulation licence.  Secondly, the IC models will usually be timing models, which are slow and can make functional and debug testing long and laborious. Usually its better just to get hold of your write your own behavioural model at the bus level, rather than the whole chip.  Have a read up on transaction modelling. You can use functions, procedures, protected types and the like to create very fast running simulation models of interfaces. Many of these may already exist in the UVM libraries, so have a look there first (but again, you will probably need a mix mode licence, as UVM is based in SystemVerilog, but Modelsim will give you a VHDL interface to them).  also have a look at this: http://osvvm.org/

[Altera_Forum]

Hi, 

I got some feedback from the contacted manufacturers and they do (if at all) only provide IBIS models. Thus there seems to be no other option than to write the chip's testbench model on my own. I think this will limit my current efforts in interface simulation validation as e.g. for the stand-alone CAN-Controller I use this might take a lot of time to implement the functions given. My intention was to have the SPI I/F incl. the data evaluation tested by e.g setting a signal in the testbench that would - in real hardware - trigger the interrupt of the CAN-controller, initializing communication and finally resulting in the internal signal "within the FPGA" being set accordingly. For this the CAN-Controller must be first configured by the FPGA to enable the pin as digital I/O, trigger the interrupt on change,.. Maybe this validation has to be done by real hardware tests, either with using SignalTap, a combination of SignalTap and Logic Analyzer to probe the SPI I/F pins or by bringing the result back "out" of the FPGA via Pins, service I/F, ... Well - it is much more work if you want to (or have to) validate operation not only by doing some limited functional tests, but at the end of the day it gives a better "feeling" and trust in the design.