[VHDL] Problem with signal type "std_logic_vector(0 downto 0)"

[Altera_Forum]

Hello, 

I use IP module, where data bus width is set to '1'. In VHDL code it is declared as type "std_logic_vector(0 downto 0)", but for compiler this is not the same as "std_logic", type of signal assigned to this bus. I changed manually in the component's source code type "std_logic_vector" to "std_logic", but then Model-Sim started to cry, that somewhere in its library in the component's entity is type "std_logic_vector". Does anyone have an idea, how to fix it? Maybe there is a compiler option to ignore it?  greetings

[Altera_Forum]

No you need to change the signal type to std_logic everywhere. Maybe you forgot to do the change in one place?

[Altera_Forum]

You can keep it as std_logic_vector and access your variable using parenthesis : data(0), no ?

[Altera_Forum]

--- Quote Start ---  You can keep it as std_logic_vector and access your variable using parenthesis : data(0), no ?  --- Quote End ---    It's working. I tried data(0 downto 0) and it failed, but data(0) is ok. Thanks!

[Altera_Forum]

--- Quote Start ---  It's working. I tried data(0 downto 0) and it failed, but data(0) is ok. Thanks!  --- Quote End ---    That is because data(0 downto 0) returns a std_logic_vector of length 1. data(0) returns a std_logic  VHDL is strongly typed so it wont let you connect incorrect types without converting them properly.